W90N745CD Datasheet, PDF (91/422 Pages) Winbond – 16/32-bit ARM microcontroller

W90N745CD/W90N745CDG
Control Register (CAHCON)
Cache controller supports one Control register used to control the following operations.
y Flush I-Cache and D-Cache
y Load and lock I-Cache and D-Cache
y Unlock I-Cache and D-Cache
y Drain write buffer
These command set bits in CAHCON register are auto-clear bits. As the end of execution, that command
set bit will be cleared to “0” automatically.
REGISTER
CAHCON
ADDRESS
0xFFF0_2004
R/W
DESCRIPTION
R/W Cache control register
RESET VALUE
0x0000_0000
31
30
23
22
15
14
7
DRWB
6
ULKS
29
21
13
5
ULKA
28
27
RESERVED
20
19
RESERVED
12
11
RESERVED
4
3
LDLK
FLHS
26
25
24
18
17
16
10
9
8
2
FLHA
1
DCAH
0
ICAH
BITS
[31:8]
[7]
[6]
[5]
[4]
RESERVED
DRWB
ULKS
ULKA
LDLK
DESCRIPTION
-
Drain write buffer
Forces write buffer data to be written to main memory.
Unlock I-Cache/D-Cache single line
Unlocks the I-Cache/D-Cache per line. Both WAY and ADDR bits in
CAHADR register must be specified.
Unlock I-Cache/D-Cache entirely
Unlocks the entire I-Cache/D-Cache, the lock bit “L” will be cleared
to 0.
Load and Lock I-Cache/D-Cache
Loads the instruction or data from external memory and locks into
cache. Both WAY and ADDR bits in CAHADR register must be
specified.
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