W90N745CD Datasheet, PDF (74/422 Pages) Winbond – 16/32-bit ARM microcontroller

W90N745CD/W90N745CDG
Timing Control Registers （SDTIME0/1）
W90N745 offers the flexible timing control registers to control the generation and processing of the
control signals and can achieve you use different speed of SDRAM
REGISTER
SDTIME0
SDTIME1
ADDRESS
0xFFF0_1010
0xFFF0_1014
R/W
DESCRIPTION
R/W SDRAM bank 0 timing control register
R/W SDRAM bank 1 timing control register
RESET VALUE
0x0000_0000
0x0000_0000
31
30
23
22
15
14
7
6
tRDL
29
21
13
RESERVED
5
28
27
RESERVED
20
19
RESERVED
12
11
4
3
tRP
26
25
24
18
17
16
10
9
8
tRCD
2
1
0
tRAS
BITS
[31:11]
[10:8]
[7:6]
RESERVED
tRCD
tRDL
DESCRIPTION
-
SDRAM bank 0/1, /RAS to /CAS delay
tRCD [10:8]
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
MCLK
1
2
3
4
5
6
7
8
SDRAM bank 0/1, Last data in to pre-charge command
tRDL [7:6]
MCLK
0
0
1
0
1
2
1
0
3
1
1
4
Publication Release Date: September 22, 2006
- 69 -
Revision A2