W90N745CD Datasheet, PDF (388/422 Pages) Winbond – 16/32-bit ARM microcontroller

W90N745CD/W90N745CDG
PS2 Host Controller Status Register (PS2_STS)
REGISTER
PS2STS
ADDRESS
R/W
0xFFF8_9004 R/W
DESCRIPTION
Status register
RESET VALUE
0x0000_0000
31
30
23
22
15
14
7
6
RESERVED
29
28
27
26
25
RESERVED
21
20
19
18
17
RESERVED
13
12
11
10
9
RESERVED
5
4
3
2
1
TX_err TX_IRQ
RESERVED
24
16
8
0
RX_IRQ
BITS
[31:6]
[5]
[4]
[3:1]
[0]
RESERVED
TX_err
TX_IRQ
RX_IRQ
DESCRIPTIONS
-
This Transmit Error Status bit indicates software that device
doesn’t response ACK after Host wrote a command to it.
This bit is valid when TX_IRQ is asserted. It will automatically
reset after software starts next command writing process.
This bit is read only.
This Transmit Complete Interrupt bit indicates software that
the process of Host controller writing command to device is
finished. Software needs to write one to this bit to clear this
interrupt.
Reserved
This Receive Interrupt bit indicates software that Host
controller receives one byte data from device. This data is
stored at PS2_SCANCODE register. Software needs to write
one to this bit to clear this interrupt after reading receiving
data in RX_SCAN_CODE register. Note that the reception of
the Extend (0xE0) and Release (0xF0) scan code will not
cause an interrupt by host. The case of the shift key codes
will be determined by the TRAP_SHIFT bit of PS2_CMD
register.
Publication Release Date: September 22, 2006
- 383 -
Revision A2