W90N745CD Datasheet, PDF (127/422 Pages) Winbond – 16/32-bit ARM microcontroller

W90N745CD/W90N745CDG
MII Management Control and Address Register (MIIDA)
The EMC provides MII management function to access the control and status registers of the external
PHY. The MIIDA register is used to keep the MII management command information, like the register
address, external PHY address, MDC clocking rate, read/write etc.
REGISTER ADDRESS
MIIDA 0xFFF0_3098
R/W
R/W
DESCRIPTION
MII Management Control and Address
Register
RESET VALUE
0x0090_0000
31
30
29
23
22
21
MDCCR
15
14
13
Reserved
7
6
5
Reserved
28
27
Reserved
20
19
MDCON
12
11
4
3
26
25
18
PreSP
10
PHYAD
2
PHYRAD
17
BUSY
9
1
24
16
Write
8
0
BITS
[31:24]
[23:20]
[19]
Reserved
MDCCR
MDC
DESCRIPTIONS
-
The MDC Clock Rating controls the MDC clock rating for MII
Management I/F.
Depend on the IEEE Std. 802.3 clause 22.2.2.11, the minimum
period for MDC shall be 400ns. In other words, the maximum
frequency for MDC is 2.5MHz. The MDC is divided from the AHB bus
clock, the HCLK. Consequently, for different HCLKs the different
ratios are required to generate appropriate MDC clock.
The following table shows relationship between HCLK and MDC
clock in different MDCCR configurations. The T_HCLK indicates the
period of HCLK.
The MDC Clock ON Always controls the MDC clock generation. If the
MDCON is set to high, the MDC clock actives always. Otherwise, the
MDC will only active while S/W issues a MII management command.
1’b0: The MDC clock will only active while S/W issues a MII
management command.
1’b1: The MDC clock actives always.
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