W90N745CD Datasheet, PDF (285/422 Pages) Winbond – 16/32-bit ARM microcontroller

W90N745CD/W90N745CDG
Interrupt Control Functions
IIR [3:0]
---1
0110
0100
1100
0010
PRIORITY
--
Highest
Second
Second
Third
INTERRUPT TYPE
None
Receiver Line Status
(Irpt_RLS)
Received Data
Available (Irpt_RDA)
Receiver FIFO Time-
out (Irpt_TOUT)
Transmitter Holing
Register Empty
(Irpt_THRE)
INTERRUPT SOURCE
INTERRUPT RESET
CONTROL
None
--
Overrun error, parity
error, framing error, or Reading the LSR
break interrupt
Receiver FIFO threshold
level is reached
Receiver FIFO drops
below the threshold
level
Receiver FIFO is non-
empty and no activities
are occurred in the
receiver FIFO during the
TOR defined time
duration
Reading the RBR
Transmitter
register empty
holding
Reading the IIR (if
source of interrupt is
Irpt_THRE)
or
writing into the THR
0000
Fourth
MODEM Status
(Irpt_MOS)
The CTS bits are changing ^{Reading the MSR}
state .
(optional)
Note: These definitions of bit 7, bit 6, bit 5, and bit 4 are different from the 16550.
HSUART FIFO Control Register (HSUART_FCR)
REGISTER OFFSET R/W
HSUART_FCR 0x08
W
DESCRIPTION
FIFO Control Register
31
30
29
23
22
21
15
14
13
7
6
5
RFITL
28
27
26
Reserved
20
19
18
Reserved
12
11
10
Reserved
4
3
2
DMS
TFR
RESET VALUE
Undefined
25
24
17
16
9
8
1
RFR
0
FME
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