W90N745CD Datasheet, PDF (19/422 Pages) Winbond – 16/32-bit ARM microcontroller

W90N745CD/W90N745CDG
Table 5.1 W90N745 Pins Description, continued
PIN NAME IO TYPE
Ethernet Interface
PHY_MDC /
IOU
GPIO [29] /
KPROW [1]
PHY_MDIO /
IO
GPIO [28] /
KPROW [0]
PHY_TXD [1:0] /
GPIO [27:26] /
IOU
KPCOL [7:6]
PHY_TXEN /
IOU
GPIO [25] /
KPCOL [5]
PHY_REFCLK /
IOS
GPIO [24] /
KPCOL [4]
PHY_RXD [1:0] /
GPIO [23:22] /
IOS
KPCOL [3:2]
PHY_CRSDV /
IOS
GPIO [21] /
KPCOL [1]
PHY_RXERR /
IOS
GPIO [20] /
KPCOL [0]
DESCRIPTION
RMII Management Data Clock for Ethernet. It is the reference clock of MDIO.
Each MDIO data will be latched at the rising edge of MDC clock.
General Programmable In/Out Port [29]
Keypad ROW[1] scan output.
RMII Management Data I/O for Ethernet. It is used to transfer RMII control and
status information between PHY and MAC.
General Programmable In/Out Port [28]
Keypad ROW[0] scan output.
2-bit Transmit Data bus for Ethernet.
General programmable In/Out Port [27:26]
Keypad column input [7:6], active low
PHY_TXEN shall be asserted synchronously with the first 2-bit of the preamble
and shall remain asserted while all di-bits to be transmitted are presented. Of
course, it is synchronized with PHY_REFCLK.
General Programmable In/Out Port [25]
Keypad column input [5], active low
Reference Clock. The clock shall be 50MHz +/- 50 ppm with minimum 35%
duty cycle at high or low state.
General Programmable In/Out port [24]
Keypad column input [4], active low
2-bit Receive Data bus for Ethernet.
General Programmable In/Out Port [23:22]
Keypad column input [3:2], active low
Carrier Sense / Receive Data Valid for Ethernet. The PHY_CRSDV shall be
asserted by PHY when the receive medium is non-idle. Loss of carrier shall
result in the de-assertion of PHY_CRSDV synchronous to the cycle of
PHY_REFCLK, and only on 2-bit receive data boundaries.
General Programmable In/Out port [21]
Keypad column input [1], active low
Receive Data Error for Ethernet. It indicates a data error detected by PHY.The
assertion should be lasted for longer than a period of PHY_REFCLK. When
PHY_RXERR is asserted, the MAC will report a CRC error.
General programmable In/Out port [20]
Keypad column input [0], active low
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