W90N745CD Datasheet, PDF (135/422 Pages) Winbond – 16/32-bit ARM microcontroller

W90N745CD/W90N745CDG
MAC Interrupt Enable Register (MIEN)
The MIEN controls the enable of EMC interrupt status to generate interrupt. Two interrupts, RXINTR
for frame reception and TXINTR for frame transmission, are generated from EMC to CPU.
REGISTER
MIEN
ADDRESS R/W
DESCRIPTION
0xFFF0_30AC R/W MAC Interrupt Enable Register
RESET VALUE
0x0000_0000
31
23
EnTDU
15
Reserved
7
EnMMP
30
22
EnLC
14
EnCFR
6
EnRP
29
28
27
Reserved
21
20
19
EnTXABT EnNCS EnEXDEF
13
12
11
Reserved
EnRxBErr
5
4
3
EnALIE EnRXGD EnPTLE
26
18
EnTXCP
10
EnRDU
2
EnRXOV
25
17
EnTXEMP
9
EnDEN
1
EnCRCE
24
EnTxBErr
16
EnTXINTR
8
EnDFO
0
EnRXINTR
BITS
[31:25]
[24]
[23]
DESCRIPTIONS
Reserved -
EnTxBErr
The Enable Transmit Bus Error Interrupt controls the TxBErr
interrupt generation. If TxBErr of MISTA register is set, and both
EnTxBErr and EnTXINTR are enabled, the EMC generates the Tx
interrupt to CPU. If EnTxBErr or EnTXINTR is disabled, no Tx interrupt
is generated to CPU even the TxBErr of MISTA register is set.
1’b0: TxBErr of MISTA register is masked from Tx interrupt generation.
1’b1: TxBErr of MISTA register can participate in Tx interrupt
generation.
EnTDU
The Enable Transmit Descriptor Unavailable Interrupt controls the
TDU interrupt generation. If TDU of MISTA register is set, and both
EnTDU and EnTXINTR are enabled, the EMC generates the Tx
interrupt to CPU. If EnTDU or EnTXINTR is disabled, no Tx interrupt is
generated to CPU even the TDU of MISTA register is set.
1’b0: TDU of MISTA register is masked from Tx interrupt generation.
1’b1: TDU of MISTA register can participate in Tx interrupt generation.
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