W90N745CD Datasheet, PDF (267/422 Pages) Winbond – 16/32-bit ARM microcontroller

W90N745CD/W90N745CDG
y Line break generation and detection
y False start bit detection
y Full prioritized interrupt system controls
y Loop back mode for internal diagnostic testing
6.10.5.1.
UART Control Registers Map
R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written
REGISTER OFFSET R/W
DESCRIPTION
UART_RBR 0x00
R _{Receive Buffer Register (DLAB = 0)}
UART_THR 0x00
W _{Transmit Holding Register (DLAB = 0)}
UART_IER
0x04 ^R/W Interrupt Enable Register (DLAB = 0)
UART_DLL
0x00
Divisor Latch Register (LS)
R/W
(DLAB = 1)
UART_DLM
0x04
Divisor Latch Register (MS)
R/W
(DLAB = 1)
UART_IIR
0x08
R _{Interrupt Identification Register}
UART_FCR 0x08
W _{FIFO Control Register}
UART_LCR 0x0C ^R/W Line Control Register
UART_MCR 0x10 R/W Modem Control Register (Optional)
UART_LSR 0x14
R Line Status Register
UART_MSR 0x18
R MODEM Status Register (Optional)
UART_TOR 0x1C R/W Time Out Register
RESET VALUE
Undefined
Undefined
0x0000_0000
0x0000_0000
0x0000_0000
0x8181_8181
Undefined
0x0000_0000
0x0000_0000
0x6060_6060
0x0000_0000
0x0000_0000
Note: Real register address = 0xFFF8_0000+ (UART number – 1) * (0x0100) + offset
Note: All of these registers are implemented 8-bit in UART design and it will be repeated 4 times
before send to APB bus. For example, when ARM CPU read register UARTn_BRR, ARM CPU will get
UART0_RBR = {RBR[7:0], RBR[7:0], RBR[7:0], RBR[7:0]}.
UART Receive Buffer Register (UART_RBR)
REGISTER
UART_RBR
OFFSET
0x00
R/W
DESCRIPTION
R Receive Buffer Register (DLAB = 0)
RESET VALUE
Undefined
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