W90N745CD Datasheet, PDF (291/422 Pages) Winbond – 16/32-bit ARM microcontroller

W90N745CD/W90N745CDG
HSUART Modem Status Register (HSUART_MSR)
REGISTER OFFSET R/W
HSUART_MSR 0x18 R
DESCRIPTION
MODEM Status Register (Optional)
RESET VALUE
0x0000_0000
31
30
29
23
22
21
15
14
13
7
6
5
Reserved
28
27
26
25
Reserved
20
19
18
17
Reserved
12
11
10
9
Reserved
4
3
2
1
CTS#
Reserved
24
16
8
0
DCTS
BITS
DESCRIPTIONS
[31:5] Reserved -
Complement version of clear to send (CTS#) input
[4]
CTS#
(This bit is selected by IP)
[3:1] Reserved -
CTS# State Change
[0]
DCTS
(This bit is selected by IP)
This bit is set whenever CTS# input has changed state, and it will be reset if
the CPU reads the MSR.
Whenever any of MSR [0] is set to logic 1, a Modem Status Interrupt is generated if IER[3]=1. Writing
MSR is a null operation (not suggested).
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