W90N745CD Datasheet, PDF (18/422 Pages) Winbond – 16/32-bit ARM microcontroller

W90N745CD/W90N745CDG
5. PIN DESCRIPTION
Table 5.1 W90N745 Pins Description
PIN NAME IO TYPE
DESCRIPTION
Clock & Reset
EXTAL (15M)
XTAL (15M)
nRESET
I
15MHz External Clock / Crystal Input
O 15MHz Crystal Output
IS System Reset, active-low
JTAG Interface
TMS
TDI
TDO
TCK
nTRST
IUS JTAG Test Mode Select, internal pull-up with 70K ohm
IUS JTAG Test Data in, internal pull-up with 70K ohm
O JTAG Test Data out
IDS JTAG Test Clock, internal pull-down with 58K ohm
IUS JTAG Reset, active-low, internal pull-up with 70K ohm
External Bus Interface
A [20:18]
A [17:0]
D [15:0]
nWBE [1:0] /
SDQM [1:0]
nSCS [1:0]
nSRAS
nSCAS
MCKE
nSWE
MCLK
nWAIT /
GPIO[30] /
nIRQ3
nBTCS
nECS [3:0]
nOE
O Address Bus (MSB) of external memory and IO devices.
IOS Address Bus of external memory and IO devices.
IOS Data Bus (LSB) of external memory and IO device.
Write Byte Enable for specific device (nECS [1:0]).
IOS
Data Bus Mask signal for SDRAM (nSCS [1:0]), active-low.
O SDRAM chip select for two external banks, active-low.
O Row Address Strobe for SDRAM, active-low.
O Column Address Strobe for SDRAM, active-low.
O SDRAM Clock Enable, active-high
O SDRAM Write Enable, active-low
O System Master Clock Out, SDRAM clock, output with slew-rate control
External Wait, active-low. This pin indicates that the external devices need
more active cycle during access operation.
IUS
General Programmable In/Out Port GPIO[30]. If memory and IO devices in EBI
do not need wait request, it can be configured as GPIO[30] or nIRQ3.
O ROM/Flash Chip Select, active-low.
IO External I/O Chip Select, active-low.
O ROM/Flash, External Memory Output Enable, active-low.
Publication Release Date: September 22, 2006
- 13 -
Revision A2