W90N745CD Datasheet, PDF (272/422 Pages) Winbond – 16/32-bit ARM microcontroller

W90N745CD/W90N745CDG
Table 6.10.6 Interrupt Control Functions
IIR [3:0] PRIORITY
INTERRUPT
TYPE
INTERRUPT SOURCE
INTERRUPT RESET
CONTROL
---1
--
None
None
--
0110
Highest
Receiver Line
Status (Irpt_RLS)
Overrun error, parity error,
framing error, or break
interrupt
Reading the LSR
0100
Second
Received Data
Available
(Irpt_RDA)
Receiver FIFO
level is reached
threshold
Receiver FIFO drops
below the threshold
level
1100
Second
Receiver FIFO
Time-out
(Irpt_TOUT)
Receiver FIFO is non-empty
and no activities are
occurred in the receiver
FIFO during the TOR
defined time duration
Reading the RBR
0010
Third
Transmitter
Holing Register
Empty
(Irpt_THRE)
Transmitter holding register
empty
Reading the IIR (if
source of interrupt is
Irpt_THRE) or writing
into the THR
0000
Fourth
MODEM Status
(Irpt_MOS)
The CTS, DSR, or DCD bits
are changing state or the RI Reading the MSR
bit is changing from high to _(optional)
low.
Note: These definitions of bit 7, bit 6, bit 5, and bit 4 are different from the 16550
UART FIFO Control Register (UART_FCR)
REGISTER OFFSET
UART_FCR 0x08
R/W
DESCRIPTION
W _{FIFO Control Register}
RESET VALUE
Undefined
31
30
23
22
15
14
7
6
RFITL
29
28
27
Reserved
21
20
19
Reserved
13
12
11
Reserved
5
4
3
RESERVED
DMS
26
18
10
2
TFR
25
17
9
1
RFR
24
16
8
0
FME
Publication Release Date: September 22, 2006
- 267 -
Revision A2