W90N745CD Datasheet, PDF (148/422 Pages) Winbond – 16/32-bit ARM microcontroller

W90N745CD/W90N745CDG
BITS
DESCRIPTIONS
[31:12] Reserved -
The Transmission Halted high indicates the next normal packet transmission
[11]
TXHA
process will be halted because the bit TXON of MCMDR is disabled be S/W.
1’b0: Next normal packet transmission process will go on.
1’b1: Next normal packet transmission process will be halted.
The Signal Quality Error high indicates the SQE error found at end of packet
transmission on 10Mbps half-duplex mode. The SQE error check will only be
[10]
SQE
done while both bit EnSQE of MCMDR is enabled and EMC is operating on
10Mbps half-duplex mode.
1’b0: No SQE error found at end of packet transmission.
1’b0: SQE error found at end of packet transmission.
The Transmission Paused high indicates the next normal packet
transmission process will be paused temporally because EMC received a
[9]
PAU
PAUSE control frame, or S/W set bit SDPZ of MCMDR and make EMC to
transmit a PAUSE control frame out.
1’b0: Next normal packet transmission process will go on.
1’b1: Next normal packet transmission process will be paused.
The Deferred Transmission high indicates the packet transmission has
deferred once. The DEF is only available while EMC is operating on half-
[8]
DEF duplex mode.
1’b0: Packet transmission doesn’t defer.
1’b1: Packet transmission has deferred once.
The Collision Count indicates the how many collision occurred consecutively
[7:4]
CCNT during a packet transmission. If the packet incurred 16 consecutive collisions
during transmission, the CCNT will be 4’h0 and bit TXABT will be set to 1.
[3] Reserved -
The RxFIFO Full indicates the RxFIFO is full due to four 64-byte packets are
[2]
RFFull
kept in RxFIFO and the following incoming packet will be dropped.
1’b0: The RxFIFO is not full.
1’b1: The RxFIFO is full and the following incoming packet will be dropped.
The Receive Halted high indicates the next normal packet reception process
[1]
RXHA
will be halted because the bit RXON of MCMDR is disabled be S/W.
1’b0: Next normal packet reception process will go on.
1’b1: Next normal packet reception process will be halted.
The Control Frame Received high indicates EMC receives a flow control
[0]
CFR
frame. The CFR only available while EMC is operating on full duplex mode.
1’b0: The EMC doesn’t receive the flow control frame.
1’b1: The EMC receives a flow control frame.
Publication Release Date: September 22, 2006
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Revision A2