W90N745CD Datasheet, PDF (141/422 Pages) Winbond – 16/32-bit ARM microcontroller

W90N745CD/W90N745CDG
MAC Interrupt Status Register (MISTA)
The MISTA keeps much EMC statuses, like frame transmission and reception status, internal FIFO
status and also NATA processing status. The statuses kept in MISTA will trigger the reception or
transmission interrupt. The MISTA is a write clear register and write 1 to corresponding bit clears the
status and also clears the interrupt.
REGISTER
ADDRESS R/W
DESCRIPTION
MISTA 0xFFF0_30B0 R/W MAC Interrupt Status Register
RESET VALUE
0x0000_0000
31
23
TDU
15
Reserved
7
MMP
30
22
LC
14
CFR
6
RP
29
28
Reserved
21
20
TXABT NCS
13
12
Reserved
5
4
ALIE
RXGD
27
19
EXDEF
11
RxBErr
3
PTLE
26
18
TXCP
10
RDU
2
RXOV
25
17
TXEMP
9
DENI
1
CRCE
24
TxBErr
16
TXINTR
8
DFOI
0
RXINTR
BITS
[31:25]
[24]
[23]
Reserved
TxBErr
TDU
DESCRIPTIONS
-
The Transmit Bus Error Interrupt high indicates the memory
controller replies ERROR response while EMC access system
memory through TxDMA during packet transmission process. Reset
EMC is recommended while TxBErr status is high.
If the TxBErr is high and EnTxBErr of MIEN register is enabled, the
TxINTR will be high. Write 1 to this bit clears the TxBErr status.
1’b0: No ERROR response is received.
1’b1: ERROR response is received.
The Transmit Descriptor Unavailable Interrupt high indicates that
there is no available Tx descriptor for packet transmission and
TxDMA will stay at Halt state. Once, the TxDMA enters the Halt
state, S/W must issues a write command to TSDR register to make
TxDMA leave Halt state while new Tx descriptor is available.
If the TDU is high and EnTDU of MIEN register is enabled, the
TxINTR will be high. Write 1 to this bit clears the TDU status.
1’b0: Tx descriptor is available.
1’b1: Tx descriptor is unavailable.
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