W90N745CD Datasheet, PDF (340/422 Pages) Winbond – 16/32-bit ARM microcontroller

W90N745CD/W90N745CDG
GPIO Interrupt Configuration Register (GPIO_XICFG)
REGISTER
GPIO_XICFG
ADDRESS
0xFFF8_3074
R/W
DESCRIPTION
RESET VALUE
R/W Extend interrupt configure register 0xXXXX_XX00
31
30
23
22
15
14
7
EnIRQ3
6
DBE3
29
28
27
RESERVED
21
20
19
RESERVED
13
12
11
RESERVED
5
4
3
ISTYPE3
EnIRQ2
26
18
10
2
DBE2
25
24
17
16
9
8
1
0
ISTYPE2
BITS
[31:8]
[7]
[6]
[5:4]
DESCRIPTION
RESERVED -
Enable nIRQ3
Setting this bit 1 to enable nIRQ3.
EnIRQ3
1 = Enable nIRQ3
0 = Disable nIRQ3
The AIC interrupt channel 31 is reserved for nIRQ3 and nIRQ2 (wired-OR),
if this bit is set and nIRQ3 occur, then it will send an interrupt request
signal into AIC module.
Debounce circuit enable for nIRQ3
(alternative function of nWAIT pin)
DBE3
The nIRQ3 shares the same debounce circuit with nIRQ[3:0], software can
configure debounce sampling time in GPIO_DEBNCE control register.
DBE3 function is the same as DBE0 in GPIO_DBENCE register.
1 = Enable debounce
0 = Disable debounce
nIRQ3 source type
ISTYPE3 Interrupt Source Type
ISTYPE3
2’b00
2’b01
LOW level sensitive
HIGH level sensitive
2’b10 Negative edge triggered
2’b11 Positive edge triggered
Publication Release Date: September 22, 2006
- 335 -
Revision A2