W90N745CD Datasheet, PDF (139/422 Pages) Winbond – 16/32-bit ARM microcontroller

W90N745CD/W90N745CDG
Continued.
BITS
[5]
[4]
[3]
DESCRIPTIONS
EnALIE
The Enable Alignment Error Interrupt controls the ALIE interrupt
generation. If ALIE of MISTA register is set, and both EnALIE and
EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If
EnALIE or EnTXINTR is disabled, no Rx interrupt is generated to CPU
even the ALIE of MISTA register is set.
1’b0: ALIE of MISTA register is masked from Rx interrupt generation.
1’b1: ALIE of MISTA register can participate in Rx interrupt generation.
EnRXGD
The Enable Receive Good Interrupt controls the RXGD interrupt
generation. If RXGD of MISTA register is set, and both EnRXGD and
EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If
EnRXGD or EnTXINTR is disabled, no Rx interrupt is generated to
CPU even the RXGD of MISTA register is set.
1’b0: RXGD of MISTA register is masked from Rx interrupt generation.
1’b1: RXGD of MISTA register can participate in Rx interrupt
generation.
EnPTLE
The Enable Packet Too Long Interrupt controls the PTLE interrupt
generation. If PTLE of MISTA register is set, and both EnPTLE and
EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If
EnPTLE or EnTXINTR is disabled, no Rx interrupt is generated to CPU
even the PTLE of MISTA register is set.
1’b0: PTLE of MISTA register is masked from Rx interrupt generation.
1’b1: PTLE of MISTA register can participate in Rx interrupt
generation.
The Enable Receive FIFO Overflow Interrupt controls the RXOV
interrupt generation. If RXOV of MISTA register is set, and both
EnRXOV and EnTXINTR are enabled, the EMC generates the Rx
interrupt to CPU. If EnRXOV or EnTXINTR is disabled, no Rx interrupt
is generated to CPU even the RXOV of MISTA register is set.
[2]
EnRXOV
1’b0: RXOV of MISTA register is masked from Rx interrupt generation.
1’b1: RXOV of MISTA register can participate in Rx interrupt
generation.
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