LM3S5D56 Datasheet, PDF (997/1146 Pages) Texas Instruments – Stellaris® LM3S5D56 Microcontroller

Stellaris^® LM3S5D56 Microcontroller
Register 21: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C
Register 22: PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C
Register 23: PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC
These registers provide the current set of interrupt sources that are asserted to the interrupt controller
(PWM0ISC controls the PWM generator 0 block, and so on). A bit is set if the event has occurred
and is enabled in the PWMnINTEN register; if a bit is clear, the event has not occurred or is not
enabled. These are R/W1C registers; writing a 1 to a bit position clears the corresponding interrupt
reason.
PWM0 Interrupt Status and Clear (PWM0ISC)
PWM0 base: 0x4002.8000
Offset 0x04C
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
25
Type RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
15
14
13
12
11
10
9
reserved
Type RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
24
23
reserved
RO
RO
0
0
8
7
RO
RO
0
0
22
21
20
19
18
17
16
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
6
5
4
3
2
1
0
INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO
RO R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C
0
0
0
0
0
0
0
Bit/Field
31:6
5
4
Name
reserved
INTCMPBD
INTCMPBU
Type
RO
R/W1C
R/W1C
Reset
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Comparator B Down Interrupt
Value Description
1 The INTCMPBD bits in the PWMnRIS and PWMnINTEN registers
are set, providing an interrupt to the interrupt controller.
0 No interrupt has occurred or the interrupt is masked.
This bit is cleared by writing a 1. Clearing this bit also clears the
INTCMPBD bit in the PWMnRIS register.
Comparator B Up Interrupt
Value Description
1 The INTCMPBU bits in the PWMnRIS and PWMnINTEN registers
are set, providing an interrupt to the interrupt controller.
0 No interrupt has occurred or the interrupt is masked.
This bit is cleared by writing a 1. Clearing this bit also clears the
INTCMPBU bit in the PWMnRIS register.
January 23, 2012
997
Texas Instruments-Production Data