LM3S5D56 Datasheet, PDF (7/1146 Pages) Texas Instruments – Stellaris® LM3S5D56 Microcontroller

Stellaris^® LM3S5D56 Microcontroller
12.3.3 Hardware Sample Averaging Circuit ............................................................................. 545
12.3.4 Analog-to-Digital Converter .......................................................................................... 545
12.3.5 Differential Sampling ................................................................................................... 549
12.3.6 Internal Temperature Sensor ........................................................................................ 551
12.3.7 Digital Comparator Unit ............................................................................................... 552
12.4 Initialization and Configuration ..................................................................................... 556
12.4.1 Module Initialization ..................................................................................................... 556
12.4.2 Sample Sequencer Configuration ................................................................................. 557
12.5 Register Map .............................................................................................................. 557
12.6 Register Descriptions .................................................................................................. 559
13 Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 618
13.1 Block Diagram ............................................................................................................ 619
13.2 Signal Description ....................................................................................................... 619
13.3 Functional Description ................................................................................................. 620
13.3.1 Transmit/Receive Logic ............................................................................................... 620
13.3.2 Baud-Rate Generation ................................................................................................. 621
13.3.3 Data Transmission ...................................................................................................... 621
13.3.4 Serial IR (SIR) ............................................................................................................. 622
13.3.5 ISO 7816 Support ....................................................................................................... 623
13.3.6 LIN Support ................................................................................................................ 623
13.3.7 FIFO Operation ........................................................................................................... 625
13.3.8 Interrupts .................................................................................................................... 625
13.3.9 Loopback Operation .................................................................................................... 626
13.3.10 DMA Operation ........................................................................................................... 626
13.4 Initialization and Configuration ..................................................................................... 627
13.5 Register Map .............................................................................................................. 628
13.6 Register Descriptions .................................................................................................. 629
14 Synchronous Serial Interface (SSI) .................................................................... 674
14.1 Block Diagram ............................................................................................................ 675
14.2 Signal Description ....................................................................................................... 675
14.3 Functional Description ................................................................................................. 676
14.3.1 Bit Rate Generation ..................................................................................................... 676
14.3.2 FIFO Operation ........................................................................................................... 676
14.3.3 Interrupts .................................................................................................................... 677
14.3.4 Frame Formats ........................................................................................................... 678
14.3.5 DMA Operation ........................................................................................................... 685
14.4 Initialization and Configuration ..................................................................................... 686
14.5 Register Map .............................................................................................................. 687
14.6 Register Descriptions .................................................................................................. 688
15 Inter-Integrated Circuit (I²C) Interface ................................................................ 716
15.1 Block Diagram ............................................................................................................ 717
15.2 Signal Description ....................................................................................................... 717
15.3 Functional Description ................................................................................................. 717
15.3.1 I²C Bus Functional Overview ........................................................................................ 718
15.3.2 Available Speed Modes ............................................................................................... 720
15.3.3 Interrupts .................................................................................................................... 721
15.3.4 Loopback Operation .................................................................................................... 722
15.3.5 Command Sequence Flow Charts ................................................................................ 722
January 23, 2012
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