LM3S5D56 Datasheet, PDF (805/1146 Pages) Texas Instruments – Stellaris® LM3S5D56 Microcontroller

Stellaris^® LM3S5D56 Microcontroller
Table 17-1. USB Signals (64LQFP) (continued)
Pin Name
Pin Number Pin Mux / Pin Pin Type Buffer Type^a Description
Assignment
USB0DP
46
fixed
I/O
Analog Bidirectional differential data pin (D+ per USB
specification) for USB0.
USB0EPEN
14
PC5 (6)
O
25
PA6 (8)
47
PB2 (8)
TTL
Optionally used in Host mode to control an external
power source to supply power to the USB bus.
USB0ID
41
PB0
I
Analog This signal senses the state of the USB ID signal.
The USB PHY enables an integrated pull-up, and
an external element (USB connector) indicates the
initial state of the USB controller (pulled down is
the A side of the cable and pulled up is the B side).
USB0PFLT
6
PE0 (9)
I
15
PC6 (7)
16
PC7 (6)
26
PA7 (8)
27
PB3 (8)
TTL
Optionally used in Host mode by an external power
source to indicate an error state by that power
source.
USB0RBIAS
48
fixed
O
Analog 9.1-kΩ resistor (1% precision) used internally for
USB analog circuitry.
USB0VBUS
42
PB1
I/O
Analog This signal is used during the session request
protocol. This signal allows the USB PHY to both
sense the voltage level of VBUS, and pull up VBUS
momentarily during VBUS pulsing.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
17.3 Functional Description
Note:
A 9.1-kΩ resistor should be connected between the USB0RBIAS and ground. The 9.1-kΩ
resistor should have a 1% tolerance and should be located in close proximity to the
USB0RBIAS pin. Power dissipation in the resistor is low, so a chip resistor of any geometry
may be used.
The Stellaris USB controller provides full OTG negotiation by supporting both the session request
protocol (SRP) and the host negotiation protocol (HNP). The session request protocol allows devices
on the B side of a cable to request the A side device turn on VBUS. The host negotiation protocol
is used after the initial session request protocol has powered the bus and provides a method to
determine which end of the cable will act as the Host controller. When the device is connected to
non-OTG peripherals or devices, the controller can detect which cable end was used and provides
a register to indicate if the controller should act as the Host or the Device controller. This indication
and the mode of operation are handled automatically by the USB controller. This auto-detection
allows the system to use a single A/B connector instead of having both A and B connectors in the
system and supports full OTG negotiations with other OTG devices.
In addition, the USB controller provides support for connecting to non-OTG peripherals or Host
controllers. The USB controller can be configured to act as either a dedicated Host or Device, in
which case, the USB0VBUS and USB0ID signals can be used as GPIOs. However, when the USB
controller is acting as a self-powered Device, a GPIO input or analog comparator input must be
connected to VBUS and configured to generate an interrupt when the VBUS level drops. This
interrupt is used to disable the pullup resistor on the USB0DP signal.
Note: When the USB module is in operation, MOSC must be the clock source, either with or
without using the PLL, and the system clock must be at least 30 MHz.
January 23, 2012
805
Texas Instruments-Production Data