LM3S5D56 Datasheet, PDF (11/1146 Pages) Texas Instruments – Stellaris® LM3S5D56 Microcontroller

Stellaris^® LM3S5D56 Microcontroller
List of Figures
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Stellaris LM3S5D56 Microcontroller High-Level Block Diagram ............................... 44
CPU Block Diagram ............................................................................................. 65
TPIU Block Diagram ............................................................................................ 66
Cortex-M3 Register Set ........................................................................................ 68
Bit-Band Mapping ................................................................................................ 88
Data Storage ....................................................................................................... 89
Vector Table ........................................................................................................ 95
Exception Stack Frame ........................................................................................ 97
SRD Use Example ............................................................................................. 111
JTAG Module Block Diagram .............................................................................. 172
Test Access Port State Machine ......................................................................... 175
IDCODE Register Format ................................................................................... 181
BYPASS Register Format ................................................................................... 181
Boundary Scan Register Format ......................................................................... 182
Basic RST Configuration .................................................................................... 186
External Circuitry to Extend Power-On Reset ....................................................... 186
Reset Circuit Controlled by Switch ...................................................................... 187
Power Architecture ............................................................................................ 190
Main Clock Tree ................................................................................................ 193
Hibernation Module Block Diagram ..................................................................... 285
Using a Crystal as the Hibernation Clock Source ................................................. 287
Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON
Mode ................................................................................................................ 288
Internal Memory Block Diagram .......................................................................... 310
μDMA Block Diagram ......................................................................................... 357
Example of Ping-Pong μDMA Transaction ........................................................... 363
Memory Scatter-Gather, Setup and Configuration ................................................ 365
Memory Scatter-Gather, μDMA Copy Sequence .................................................. 366
Peripheral Scatter-Gather, Setup and Configuration ............................................. 368
Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 369
Digital I/O Pads ................................................................................................. 419
Analog/Digital I/O Pads ...................................................................................... 420
GPIODATA Write Example ................................................................................. 421
GPIODATA Read Example ................................................................................. 421
GPTM Module Block Diagram ............................................................................ 468
Timer Daisy Chain ............................................................................................. 472
Input Edge-Count Mode Example ....................................................................... 474
16-Bit Input Edge-Time Mode Example ............................................................... 475
16-Bit PWM Mode Example ................................................................................ 477
WDT Module Block Diagram .............................................................................. 514
Implementation of Two ADC Blocks .................................................................... 539
ADC Module Block Diagram ............................................................................... 540
ADC Sample Phases ......................................................................................... 543
Doubling the ADC Sample Rate .......................................................................... 544
Skewed Sampling .............................................................................................. 544
Sample Averaging Example ............................................................................... 545
January 23, 2012
11
Texas Instruments-Production Data