LM3S5D56 Datasheet, PDF (179/1146 Pages) Texas Instruments – Stellaris® LM3S5D56 Microcontroller

Stellaris^® LM3S5D56 Microcontroller
4.5.1.1
4.5.1.2
4.5.1.3
Table 4-3. JTAG Instruction Register Commands
IR[3:0]
0x0
0x1
0x2
0x8
0xA
0xB
0xE
0xF
All Others
Instruction
EXTEST
INTEST
SAMPLE / PRELOAD
ABORT
DPACC
APACC
IDCODE
BYPASS
Reserved
Description
Drives the values preloaded into the Boundary Scan Chain by the
SAMPLE/PRELOAD instruction onto the pads.
Drives the values preloaded into the Boundary Scan Chain by the
SAMPLE/PRELOAD instruction into the controller.
Captures the current I/O values and shifts the sampled values out of the
Boundary Scan Chain while new preload data is shifted in.
Shifts data into the ARM Debug Port Abort Register.
Shifts data into and out of the ARM DP Access Register.
Shifts data into and out of the ARM AC Access Register.
Loads manufacturing information defined by the IEEE Standard 1149.1 into
the IDCODE chain and shifts it out.
Connects TDI to TDO through a single Shift Register chain.
Defaults to the BYPASS instruction to ensure that TDI is always connected
to TDO.
EXTEST Instruction
The EXTEST instruction is not associated with its own Data Register chain. Instead, the EXTEST
instruction uses the data that has been preloaded into the Boundary Scan Data Register using the
SAMPLE/PRELOAD instruction. When the EXTEST instruction is present in the Instruction Register,
the preloaded data in the Boundary Scan Data Register associated with the outputs and output
enables are used to drive the GPIO pads rather than the signals coming from the core. With tests
that drive known values out of the controller, this instruction can be used to verify connectivity. While
the EXTEST instruction is present in the Instruction Register, the Boundary Scan Data Register can
be accessed to sample and shift out the current data and load new data into the Boundary Scan
Data Register.
INTEST Instruction
The INTEST instruction is not associated with its own Data Register chain. Instead, the INTEST
instruction uses the data that has been preloaded into the Boundary Scan Data Register using the
SAMPLE/PRELOAD instruction. When the INTEST instruction is present in the Instruction Register,
the preloaded data in the Boundary Scan Data Register associated with the inputs are used to drive
the signals going into the core rather than the signals coming from the GPIO pads. With tests that
drive known values into the controller, this instruction can be used for testing. It is important to note
that although the RST input pin is on the Boundary Scan Data Register chain, it is only observable.
While the INTEST instruction is present in the Instruction Register, the Boundary Scan Data Register
can be accessed to sample and shift out the current data and load new data into the Boundary Scan
Data Register.
SAMPLE/PRELOAD Instruction
The SAMPLE/PRELOAD instruction connects the Boundary Scan Data Register chain between
TDI and TDO. This instruction samples the current state of the pad pins for observation and preloads
new test data. Each GPIO pad has an associated input, output, and output enable signal. When the
TAP controller enters the Capture DR state during this instruction, the input, output, and output-enable
signals to each of the GPIO pads are captured. These samples are serially shifted out on TDO while
the TAP controller is in the Shift DR state and can be used for observation or comparison in various
tests.
January 23, 2012
179
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