LM3S5D56 Datasheet, PDF (896/1146 Pages) Texas Instruments – Stellaris® LM3S5D56 Microcontroller

Universal Serial Bus (USB) Controller
OTG A /
Host
Register 195: USB Receive Control and Status Endpoint 1 Low (USBRXCSRL1),
offset 0x116
Register 196: USB Receive Control and Status Endpoint 2 Low (USBRXCSRL2),
offset 0x126
Register 197: USB Receive Control and Status Endpoint 3 Low (USBRXCSRL3),
offset 0x136
Register 198: USB Receive Control and Status Endpoint 4 Low (USBRXCSRL4),
offset 0x146
Register 199: USB Receive Control and Status Endpoint 5 Low (USBRXCSRL5),
offset 0x156
Register 200: USB Receive Control and Status Endpoint 6 Low (USBRXCSRL6),
offset 0x166
Register 201: USB Receive Control and Status Endpoint 7 Low (USBRXCSRL7),
offset 0x176
Register 202: USB Receive Control and Status Endpoint 8 Low (USBRXCSRL8),
offset 0x186
Register 203: USB Receive Control and Status Endpoint 9 Low (USBRXCSRL9),
offset 0x196
Register 204: USB Receive Control and Status Endpoint 10 Low
(USBRXCSRL10), offset 0x1A6
Register 205: USB Receive Control and Status Endpoint 11 Low
(USBRXCSRL11), offset 0x1B6
Register 206: USB Receive Control and Status Endpoint 12 Low
(USBRXCSRL12), offset 0x1C6
Register 207: USB Receive Control and Status Endpoint 13 Low
(USBRXCSRL13), offset 0x1D6
Register 208: USB Receive Control and Status Endpoint 14 Low
(USBRXCSRL14), offset 0x1E6
Register 209: USB Receive Control and Status Endpoint 15 Low
(USBRXCSRL15), offset 0x1F6
USBRXCSRLn is an 8-bit register that provides control and status bits for transfers through the
currently selected receive endpoint.
OTG B /
Device
896
January 23, 2012
Texas Instruments-Production Data