LM3S5D56 Datasheet, PDF (887/1146 Pages) Texas Instruments – Stellaris® LM3S5D56 Microcontroller

Stellaris^® LM3S5D56 Microcontroller
Bit/Field
3
2
1
0
Name
FLUSH
ERROR
FIFONE
TXRDY
Type
R/W
R/W
R/W
R/W
Reset
0
Description
Flush FIFO
Value Description
0 No effect.
1 Flushes the latest packet from the endpoint transmit FIFO. The
FIFO pointer is reset and the TXRDY bit is cleared. The EPn bit
in the USBTXIS register is also set in this situation.
This bit may be set simultaneously with the TXRDY bit to abort the packet
that is currently being loaded into the FIFO. Note that if the FIFO is
double-buffered, FLUSH may have to be set twice to completely clear
the FIFO.
Important: ^{This bit should only be set when the TXRDY bit is set. At}
other times, it may cause data to be corrupted.
0
Error
Value Description
0 No error.
1 Three attempts have been made to send a packet and no
handshake packet has been received. The TXRDY bit is cleared,
the EPn bit in the USBTXIS register is set, and the FIFO is
completely flushed in this situation.
Software must clear this bit.
Note: This is valid only when the endpoint is operating in Bulk or
Interrupt mode.
0
FIFO Not Empty
Value Description
0 The FIFO is empty.
1 At least one packet is in the transmit FIFO.
0
Transmit Packet Ready
Value Description
0 No transmit packet is ready.
1 Software sets this bit after loading a data packet into the TX
FIFO.
This bit is cleared automatically when a data packet has been
transmitted. The EPn bit in the USBTXIS register is also set at this point.
TXRDY is also automatically cleared prior to loading a second packet
into a double-buffered FIFO.
January 23, 2012
887
Texas Instruments-Production Data