LM3S5D56 Datasheet, PDF (808/1146 Pages) Texas Instruments – Stellaris® LM3S5D56 Microcontroller

Universal Serial Bus (USB) Controller
Single-Packet Buffering
If the size of the receive endpoint FIFO is less than twice the maximum packet size for an endpoint,
only one data packet can be buffered in the FIFO and single-packet buffering is required. When a
packet is received and placed in the receive FIFO, the RXRDY and FULL bits in the USB Receive
Control and Status Endpoint n Low (USBRXCSRLn) register are set and the appropriate receive
endpoint is signaled, indicating that a packet can now be unloaded from the FIFO. After the packet
has been unloaded, the RXRDY bit must be cleared in order to allow further packets to be received.
This action also generates the acknowledge signaling to the Host controller. If the AUTOCL bit in the
USB Receive Control and Status Endpoint n High (USBRXCSRHn) register is set and a
maximum-sized packet is unloaded from the FIFO, the RXRDY and FULL bits are cleared
automatically. For packet sizes less than the maximum, RXRDY must be cleared manually.
Double-Packet Buffering
If the size of the receive endpoint FIFO is at least twice the maximum packet size for the endpoint,
two data packets can be buffered and double-packet buffering can be used. When the first packet
is received and loaded into the receive FIFO, the RXRDY bit in the USBRXCSRLn register is set
and the appropriate receive endpoint interrupt is signaled to indicate that a packet can now be
unloaded from the FIFO.
Note: The FULL bit in USBRXCSRLn is not set when the first packet is received. It is only set if
a second packet is received and loaded into the receive FIFO.
After each packet has been unloaded, the RXRDY bit must be cleared to allow further packets to be
received. If the AUTOCL bit in the USBRXCSRHn register is set and a maximum-sized packet is
unloaded from the FIFO, the RXRDY bit is cleared automatically. For packet sizes less than the
maximum, RXRDY must be cleared manually. If the FULL bit is set when RXRDY is cleared, the USB
controller first clears the FULL bit, then sets RXRDY again to indicate that there is another packet
waiting in the FIFO to be unloaded.
Note: Double-packet buffering is disabled if an endpoint’s corresponding EPn bit is set in the USB
Receive Double Packet Buffer Disable (USBRXDPKTBUFDIS) register. This bit is set
by default, so it must be cleared to enable double-packet buffering.
17.3.1.4
Scheduling
The Device has no control over the scheduling of transactions as scheduling is determined by the
Host controller. The Stellaris USB controller can set up a transaction at any time. The USB controller
waits for the request from the Host controller and generates an interrupt when the transaction is
complete or if it was terminated due to some error. If the Host controller makes a request and the
Device controller is not ready, the USB controller sends a busy response (NAK) to all requests until
it is ready.
17.3.1.5
Additional Actions
The USB controller responds automatically to certain conditions on the USB bus or actions by the
Host controller such as when the USB controller automatically stalls a control transfer or unexpected
zero length OUT data packets.
Stalled Control Transfer
The USB controller automatically issues a STALL handshake to a control transfer under the following
conditions:
1. The Host sends more data during an OUT data phase of a control transfer than was specified
in the Device request during the SETUP phase. This condition is detected by the USB controller
808
January 23, 2012
Texas Instruments-Production Data