LM3S5D56 Datasheet, PDF (24/1146 Pages) Texas Instruments – Stellaris® LM3S5D56 Microcontroller

Table of Contents
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ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 588
ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 591
ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 591
ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 591
ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 591
ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 592
ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 592
ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 592
ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 592
ADC Sample Sequence 0 Operation (ADCSSOP0), offset 0x050 ...................................... 594
ADC Sample Sequence 0 Digital Comparator Select (ADCSSDC0), offset 0x054 .............. 596
ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 598
ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 598
ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 599
ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 599
ADC Sample Sequence 1 Operation (ADCSSOP1), offset 0x070 ...................................... 601
ADC Sample Sequence 2 Operation (ADCSSOP2), offset 0x090 ..................................... 601
ADC Sample Sequence 1 Digital Comparator Select (ADCSSDC1), offset 0x074 .............. 602
ADC Sample Sequence 2 Digital Comparator Select (ADCSSDC2), offset 0x094 .............. 602
ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 604
ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 605
ADC Sample Sequence 3 Operation (ADCSSOP3), offset 0x0B0 ..................................... 606
ADC Sample Sequence 3 Digital Comparator Select (ADCSSDC3), offset 0x0B4 .............. 607
ADC Digital Comparator Reset Initial Conditions (ADCDCRIC), offset 0xD00 ..................... 608
ADC Digital Comparator Control 0 (ADCDCCTL0), offset 0xE00 ....................................... 613
ADC Digital Comparator Control 1 (ADCDCCTL1), offset 0xE04 ....................................... 613
ADC Digital Comparator Control 2 (ADCDCCTL2), offset 0xE08 ....................................... 613
ADC Digital Comparator Control 3 (ADCDCCTL3), offset 0xE0C ...................................... 613
ADC Digital Comparator Control 4 (ADCDCCTL4), offset 0xE10 ....................................... 613
ADC Digital Comparator Control 5 (ADCDCCTL5), offset 0xE14 ....................................... 613
ADC Digital Comparator Control 6 (ADCDCCTL6), offset 0xE18 ....................................... 613
ADC Digital Comparator Control 7 (ADCDCCTL7), offset 0xE1C ...................................... 613
ADC Digital Comparator Range 0 (ADCDCCMP0), offset 0xE40 ....................................... 616
ADC Digital Comparator Range 1 (ADCDCCMP1), offset 0xE44 ....................................... 616
ADC Digital Comparator Range 2 (ADCDCCMP2), offset 0xE48 ....................................... 616
ADC Digital Comparator Range 3 (ADCDCCMP3), offset 0xE4C ...................................... 616
ADC Digital Comparator Range 4 (ADCDCCMP4), offset 0xE50 ....................................... 616
ADC Digital Comparator Range 5 (ADCDCCMP5), offset 0xE54 ....................................... 616
ADC Digital Comparator Range 6 (ADCDCCMP6), offset 0xE58 ....................................... 616
ADC Digital Comparator Range 7 (ADCDCCMP7), offset 0xE5C ...................................... 616
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 618
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 630
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 632
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 635
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 637
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 638
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 639
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 640
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January 23, 2012
Texas Instruments-Production Data