LM3S5D56 Datasheet, PDF (541/1146 Pages) Texas Instruments – Stellaris® LM3S5D56 Microcontroller

Stellaris^® LM3S5D56 Microcontroller
Table 12-1. ADC Signals (64LQFP) (continued)
Pin Name
Pin Number Pin Mux / Pin Pin Type Buffer Type^a Description
Assignment
VREFA
56
PB6
I
Analog This input provides a reference voltage used to
specify the input voltage at which the ADC converts
to a maximum value. In other words, the voltage
that is applied to VREFA is the voltage with which
an AINn signal is converted to 4095. The VREFA
input is limited to the range specified in Table
24-23 on page 1084 .
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
12.3
Functional Description
The Stellaris ADC collects sample data by using a programmable sequence-based approach instead
of the traditional single or double-sampling approaches found on many ADC modules. Each sample
sequence is a fully programmed series of consecutive (back-to-back) samples, allowing the ADC
to collect data from multiple input sources without having to be re-configured or serviced by the
processor. The programming of each sample in the sample sequence includes parameters such as
the input source and mode (differential versus single-ended input), interrupt generation on sample
completion, and the indicator for the last sample in the sequence. In addition, the μDMA can be
used to more efficiently move data from the sample sequencers without CPU intervention.
12.3.1
Sample Sequencers
The sampling control and data capture is handled by the sample sequencers. All of the sequencers
are identical in implementation except for the number of samples that can be captured and the depth
of the FIFO. Table 12-2 on page 541 shows the maximum number of samples that each sequencer
can capture and its corresponding FIFO depth. Each sample that is captured is stored in the FIFO.
In this implementation, each FIFO entry is a 32-bit word, with the lower 12 bits containing the
conversion result.
Table 12-2. Samples and FIFO Depth of Sequencers
Sequencer
SS3
SS2
SS1
SS0
Number of Samples
1
4
4
8
Depth of FIFO
1
4
4
8
For a given sample sequence, each sample is defined by bit fields in the ADC Sample Sequence
Input Multiplexer Select (ADCSSMUXn) and ADC Sample Sequence Control (ADCSSCTLn)
registers, where "n" corresponds to the sequence number. The ADCSSMUXn fields select the input
pin, while the ADCSSCTLn fields contain the sample control bits corresponding to parameters such
as temperature sensor selection, interrupt enable, end of sequence, and differential input mode.
Sample sequencers are enabled by setting the respective ASENn bit in the ADC Active Sample
Sequencer (ADCACTSS) register and should be configured before being enabled. Sampling is
then initiated by setting the SSn bit in the ADC Processor Sample Sequence Initiate (ADCPSSI)
register. In addition, sample sequences may be initiated on multiple ADC modules simultaneously
using the GSYNC and SYNCWAIT bits in the ADCPSSI register during the configuration of each ADC
module. For more information on using these bits, refer to page 580.
When configuring a sample sequence, multiple uses of the same input pin within the same sequence
are allowed. In the ADCSSCTLn register, the IEn bits can be set for any combination of samples,
January 23, 2012
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Texas Instruments-Production Data