LM3S5D56 Datasheet, PDF (1064/1146 Pages) Texas Instruments – Stellaris® LM3S5D56 Microcontroller

Signal Tables
Table 22-4. Signals by Function, Except for GPIO (continued)
Function
Pin Name Pin Number Pin Type Buffer Type^a
Description
GND
10
-
Power Ground reference for logic and I/O pins.
13
24
29
36
39
44
53
60
GNDA
4
-
Power The ground reference for the analog circuits (ADC,
Analog Comparators, etc.). These are separated
from GND to minimize the electrical noise contained
on VDD from affecting the analog functions.
LDO
Power
7
-
Power Low drop-out regulator output voltage. This pin
requires an external capacitor between the pin and
GND of 1 µF or greater. The LDO pin must also be
connected to the VDDC pins at the board level in
addition to the decoupling capacitor(s).
VDD
12
-
Power Positive supply for I/O and some logic.
28
43
59
VDDA
3
-
Power The positive supply for the analog circuits (ADC,
Analog Comparators, etc.). These are separated
from VDD to minimize the electrical noise contained
on VDD from affecting the analog functions. VDDA
pins must be supplied with a voltage that meets the
specification in Table 24-2 on page 1072, regardless
of system implementation.
VDDC
9
-
Power Positive supply for most of the logic function,
23
including the processor core and most peripherals.
38
The voltage on this pin is 1.3 V and is supplied by
54
the on-chip LDO. The VDDC pins should only be
connected to the LDO pin and an external capacitor
as specified in Table 24-6 on page 1077.
IDX0
47
I
TTL
QEI module 0 index.
56
58
61
QEI
PhA0
2
I
TTL
QEI module 0 phase A.
11
62
PhB0
1
I
TTL
QEI module 0 phase B.
15
16
1064
Texas Instruments-Production Data
January 23, 2012