LM3S5D56 Datasheet, PDF (719/1146 Pages) Texas Instruments – Stellaris® LM3S5D56 Microcontroller

Stellaris^® LM3S5D56 Microcontroller
Interrupt Status (I2CSMIS) register allow start and stop conditions to be promoted to controller
interrupts (when interrupts are enabled).
15.3.1.2
Data Format with 7-Bit Address
Data transfers follow the format shown in Figure 15-4. After the START condition, a slave address
is transmitted. This address is 7-bits long followed by an eighth bit, which is a data direction bit (R/S
bit in the I2CMSA register). If the R/S bit is clear, it indicates a transmit operation (send), and if it
is set, it indicates a request for data (receive). A data transfer is always terminated by a STOP
condition generated by the master, however, a master can initiate communications with another
device on the bus by generating a repeated START condition and addressing another slave without
first generating a STOP condition. Various combinations of receive/transmit formats are then possible
within a single transfer.
Figure 15-4. Complete Data Transfer with a 7-Bit Address
SDA
MSB
LSB
R/S
ACK
MSB
LSB
ACK
SCL
Start
1
2
7
8
9
Slave address
1
2
7
8
9
Data
Stop
The first seven bits of the first byte make up the slave address (see Figure 15-5). The eighth bit
determines the direction of the message. A zero in the R/S position of the first byte means that the
master transmits (sends) data to the selected slave, and a one in this position means that the master
receives data from the slave.
Figure 15-5. R/S Bit in First Byte
MSB
LSB
R/S
Slave address
15.3.1.3
Data Validity
The data on the SDA line must be stable during the high period of the clock, and the data line can
only change when SCL is Low (see Figure 15-6).
Figure 15-6. Data Validity During Bit Transfer on the I²C Bus
SDA
SCL
Data line Change
stable of data
allowed
15.3.1.4
Acknowledge
All bus transactions have a required acknowledge clock cycle that is generated by the master. During
the acknowledge cycle, the transmitter (which can be the master or slave) releases the SDA line.
To acknowledge the transaction, the receiver must pull down SDA during the acknowledge clock
January 23, 2012
719
Texas Instruments-Production Data