LM3S5D56 Datasheet, PDF (14/1146 Pages) Texas Instruments – Stellaris® LM3S5D56 Microcontroller

Table of Contents
List of Tables
Table 1.
Table 2.
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
Table 2-5.
Table 2-6.
Table 2-7.
Table 2-8.
Table 2-9.
Table 2-10.
Table 2-11.
Table 2-12.
Table 2-13.
Table 3-1.
Table 3-2.
Table 3-3.
Table 3-4.
Table 3-5.
Table 3-6.
Table 3-7.
Table 3-8.
Table 3-9.
Table 4-1.
Table 4-2.
Table 4-3.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 5-5.
Table 5-6.
Table 5-7.
Table 5-8.
Table 6-1.
Table 6-2.
Table 6-3.
Table 7-1.
Table 7-2.
Table 7-3.
Table 8-1.
Table 8-2.
Table 8-3.
Table 8-4.
Table 8-5.
Revision History .................................................................................................. 37
Documentation Conventions ................................................................................ 41
Summary of Processor Mode, Privilege Level, and Stack Use ................................ 68
Processor Register Map ....................................................................................... 69
PSR Register Combinations ................................................................................. 74
Memory Map ....................................................................................................... 82
Memory Access Behavior ..................................................................................... 85
SRAM Memory Bit-Banding Regions .................................................................... 87
Peripheral Memory Bit-Banding Regions ............................................................... 87
Exception Types .................................................................................................. 93
Interrupts ............................................................................................................ 93
Exception Return Behavior ................................................................................... 98
Faults ................................................................................................................. 99
Fault Status and Fault Address Registers ............................................................ 100
Cortex-M3 Instruction Summary ......................................................................... 102
Core Peripheral Register Regions ....................................................................... 105
Memory Attributes Summary .............................................................................. 108
TEX, S, C, and B Bit Field Encoding ................................................................... 111
Cache Policy for Memory Attribute Encoding ....................................................... 112
AP Bit Field Encoding ........................................................................................ 112
Memory Region Attributes for Stellaris Microcontrollers ........................................ 112
Peripherals Register Map ................................................................................... 113
Interrupt Priority Levels ...................................................................................... 140
Example SIZE Field Values ................................................................................ 168
JTAG_SWD_SWO Signals (64LQFP) ................................................................. 172
JTAG Port Pins State after Power-On Reset or RST assertion .............................. 173
JTAG Instruction Register Commands ................................................................. 179
System Control & Clocks Signals (64LQFP) ........................................................ 183
Reset Sources ................................................................................................... 184
Clock Source Options ........................................................................................ 191
Possible System Clock Frequencies Using the SYSDIV Field ............................... 194
Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 194
Examples of Possible System Clock Frequencies with DIV400=1 ......................... 195
System Control Register Map ............................................................................. 200
RCC2 Fields that Override RCC Fields ............................................................... 221
Hibernate Signals (64LQFP) ............................................................................... 285
Hibernation Module Clock Operation ................................................................... 291
Hibernation Module Register Map ....................................................................... 293
Flash Memory Protection Policy Combinations .................................................... 314
User-Programmable Flash Memory Resident Registers ....................................... 318
Flash Register Map ............................................................................................ 319
μDMA Channel Assignments .............................................................................. 358
Request Type Support ....................................................................................... 360
Control Structure Memory Map ........................................................................... 361
Channel Control Structure .................................................................................. 361
μDMA Read Example: 8-Bit Peripheral ................................................................ 370
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January 23, 2012
Texas Instruments-Production Data