LM3S5D56 Datasheet, PDF (205/1146 Pages) Texas Instruments – Stellaris® LM3S5D56 Microcontroller

Stellaris^® LM3S5D56 Microcontroller
Register 3: Raw Interrupt Status (RIS), offset 0x050
This register indicates the status for system control raw interrupts. An interrupt is sent to the interrupt
controller if the corresponding bit in the Interrupt Mask Control (IMC) register is set. Writing a 1
to the corresponding bit in the Masked Interrupt Status and Clear (MISC) register clears an interrupt
status bit.
Raw Interrupt Status (RIS)
Base 0x400F.E000
Offset 0x050
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
MOSCPUPRIS USBPLLLRIS PLLLRIS
reserved
BORRIS reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:9
8
7
6
Name
reserved
MOSCPUPRIS
USBPLLLRIS
PLLLRIS
Type
RO
RO
RO
RO
Reset Description
0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
MOSC Power Up Raw Interrupt Status
Value Description
1 Sufficient time has passed for the MOSC to reach the expected
frequency. The value for this power-up time is indicated by
T_{MOSC_START}.
0 Sufficient time has not passed for the MOSC to reach the
expected frequency.
This bit is cleared by writing a 1 to the MOSCPUPMIS bit in the MISC
register.
0
USB PLL Lock Raw Interrupt Status
Value Description
1
The USB PLL timer has reached T_READY indicating that sufficient
time has passed for the USB PLL to lock.
0
The USB PLL timer has not reached T_READY.
This bit is cleared by writing a 1 to the USBPLLLMIS bit in the MISC
register.
0
PLL Lock Raw Interrupt Status
Value Description
1
The PLL timer has reached T_READY indicating that sufficient time
has passed for the PLL to lock.
0
The PLL timer has not reached T_READY.
This bit is cleared by writing a 1 to the PLLLMIS bit in the MISC register.
January 23, 2012
205
Texas Instruments-Production Data