LM3S5D56 Datasheet, PDF (676/1146 Pages) Texas Instruments – Stellaris® LM3S5D56 Microcontroller

Synchronous Serial Interface (SSI)
parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control
(GPIOPCTL) register (page 453) to assign the SSI signal to the specified GPIO port pin. For more
information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 416.
Table 14-1. SSI Signals (64LQFP)
Pin Name
Pin Number Pin Mux / Pin Pin Type Buffer Type^a Description
Assignment
SSI0Clk
19
PA2 (1)
I/O
TTL
SSI module 0 clock.
SSI0Fss
20
PA3 (1)
I/O
TTL
SSI module 0 frame.
SSI0Rx
21
PA4 (1)
I
TTL
SSI module 0 receive.
SSI0Tx
22
PA5 (1)
O
TTL
SSI module 0 transmit.
SSI1Clk
6
PE0 (2)
I/O
TTL
SSI module 1 clock.
SSI1Fss
5
PE1 (2)
I/O
TTL
SSI module 1 frame.
SSI1Rx
2
PE2 (2)
I
TTL
SSI module 1 receive.
SSI1Tx
1
PE3 (2)
O
TTL
SSI module 1 transmit.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
14.3
Functional Description
The SSI performs serial-to-parallel conversion on data received from a peripheral device. The CPU
accesses data, control, and status information. The transmit and receive paths are buffered with
internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit
and receive modes. The SSI also supports the µDMA interface. The transmit and receive FIFOs
can be programmed as destination/source addresses in the µDMA module. µDMA operation is
enabled by setting the appropriate bit(s) in the SSIDMACTL register (see page 703).
14.3.1
14.3.2
Bit Rate Generation
The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output
clock. Bit rates are supported to 2 MHz and higher, although maximum bit rate is determined by
peripheral devices.
The serial bit rate is derived by dividing down the input clock (SysClk). The clock is first divided by
an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale
(SSICPSR) register (see page 696). The clock is further divided by a value from 1 to 256, which is
1 + SCR, where SCR is the value programmed in the SSI Control 0 (SSICR0) register (see page 689).
The frequency of the output clock SSIClk is defined by:
SSIClk = SysClk / (CPSDVSR * (1 + SCR))
Note: For master mode, the system clock must be at least two times faster than the SSIClk, with
the restriction that SSIClk cannot be faster than 25 MHz. For slave mode, the system clock
must be at least 12 times faster than the SSIClk.
See “Synchronous Serial Interface (SSI)” on page 1085 to view SSI timing parameters.
FIFO Operation
14.3.2.1
Transmit FIFO
The common transmit FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. The
CPU writes data to the FIFO by writing the SSI Data (SSIDR) register (see page 693), and data is
stored in the FIFO until it is read out by the transmission logic.
676
January 23, 2012
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