LM3S5D56 Datasheet, PDF (1114/1146 Pages) Texas Instruments – Stellaris® LM3S5D56 Microcontroller

Register Quick Reference
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I2CMTPR, type R/W, offset 0x00C, reset 0x0000.0001
I2CMIMR, type R/W, offset 0x010, reset 0x0000.0000
TPR
IM
I2CMRIS, type RO, offset 0x014, reset 0x0000.0000
RIS
I2CMMIS, type RO, offset 0x018, reset 0x0000.0000
MIS
I2CMICR, type WO, offset 0x01C, reset 0x0000.0000
IC
I2CMCR, type R/W, offset 0x020, reset 0x0000.0000
Inter-Integrated Circuit (I²C) Interface
I²C Slave
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2CSOAR, type R/W, offset 0x800, reset 0x0000.0000
SFE
MFE
LPBK
I2CSCSR, type RO, offset 0x804, reset 0x0000.0000 (Read-Only Status Register)
OAR
I2CSCSR, type WO, offset 0x804, reset 0x0000.0000 (Write-Only Control Register)
FBR
TREQ RREQ
DA
I2CSDR, type R/W, offset 0x808, reset 0x0000.0000
I2CSIMR, type R/W, offset 0x80C, reset 0x0000.0000
DATA
I2CSRIS, type RO, offset 0x810, reset 0x0000.0000
STOPIM STARTIM DATAIM
I2CSMIS, type RO, offset 0x814, reset 0x0000.0000
STOPRIS STARTRIS DATARIS
I2CSICR, type WO, offset 0x818, reset 0x0000.0000
STOPMIS STARTMIS DATAMIS
Controller Area Network (CAN) Module
CAN0 base: 0x4004.0000
CANCTL, type R/W, offset 0x000, reset 0x0000.0001 (see page 774)
STOPIC STARTIC DATAIC
TEST
CCE
DAR
EIE
SIE
IE
INIT
1114
Texas Instruments-Production Data
January 23, 2012