LM3S5D56 Datasheet, PDF (293/1146 Pages) Texas Instruments – Stellaris® LM3S5D56 Microcontroller

Stellaris^® LM3S5D56 Microcontroller
4. Set the RTC Match/External Wake-Up and start the hibernation sequence by writing 0x0000.005F
to the HIBCTL register at offset 0x010.
6.5 Register Map
Table 6-3 on page 293 lists the Hibernation registers. All addresses given are relative to the Hibernation
Module base address at 0x400F.C000. Note that the system clock to the Hibernation module must
be enabled before the registers can be programmed (see page 254). There must be a delay of 3
system clocks after the Hibernation module clock is enabled before any Hibernation module registers
are accessed.
Note:
HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the
Hibernation module clock domain and have special timing requirements. Software should
make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has
elapsed. If the WRC bit is clear, any attempted write access is ignored. See “Register Access
Timing” on page 286.
Important: The Hibernation module registers are reset under two conditions:
1. A system reset when the RTCEN and the PINWEN bits in the HIBCTL register are
both cleared.
2. A cold POR, when both the V_DD and V_BAT supplies are removed.
Any other reset condition is ignored by the Hibernation module.
Table 6-3. Hibernation Module Register Map
Offset Name
Type
Reset
Description
0x000 HIBRTCC
0x004 HIBRTCM0
0x008 HIBRTCM1
0x00C HIBRTCLD
0x010 HIBCTL
0x014 HIBIM
0x018 HIBRIS
0x01C HIBMIS
0x020 HIBIC
0x024 HIBRTCT
0x030-
0x12C
HIBDATA
RO
R/W
R/W
R/W
R/W
R/W
RO
RO
R/W1C
R/W
R/W
0x0000.0000
0xFFFF.FFFF
0xFFFF.FFFF
0xFFFF.FFFF
0x8000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.7FFF
-
Hibernation RTC Counter
Hibernation RTC Match 0
Hibernation RTC Match 1
Hibernation RTC Load
Hibernation Control
Hibernation Interrupt Mask
Hibernation Raw Interrupt Status
Hibernation Masked Interrupt Status
Hibernation Interrupt Clear
Hibernation RTC Trim
Hibernation Data
See
page
294
295
296
297
298
301
303
305
307
308
309
6.6 Register Descriptions
The remainder of this section lists and describes the Hibernation module registers, in numerical
order by address offset.
January 23, 2012
293
Texas Instruments-Production Data