LM3S5D56 Datasheet, PDF (5/1146 Pages) Texas Instruments – Stellaris® LM3S5D56 Microcontroller

Stellaris^® LM3S5D56 Microcontroller
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Hibernation Module .............................................................................................. 284
6.1 Block Diagram ............................................................................................................ 285
6.2 Signal Description ....................................................................................................... 285
6.3 Functional Description ................................................................................................. 286
6.3.1 Register Access Timing ............................................................................................... 286
6.3.2 Hibernation Clock Source ............................................................................................ 286
6.3.3 System Implementation ............................................................................................... 288
6.3.4 Battery Management ................................................................................................... 288
6.3.5 Real-Time Clock .......................................................................................................... 289
6.3.6 Battery-Backed Memory .............................................................................................. 289
6.3.7 Power Control Using HIB ............................................................................................. 289
6.3.8 Power Control Using VDD3ON Mode ........................................................................... 290
6.3.9 Initiating Hibernate ...................................................................................................... 290
6.3.10 Waking from Hibernate ................................................................................................ 290
6.3.11 Interrupts and Status ................................................................................................... 290
6.4 Initialization and Configuration ..................................................................................... 291
6.4.1 Initialization ................................................................................................................. 291
6.4.2 RTC Match Functionality (No Hibernation) .................................................................... 292
6.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 292
6.4.4 External Wake-Up from Hibernation .............................................................................. 292
6.4.5 RTC or External Wake-Up from Hibernation .................................................................. 292
6.5 Register Map .............................................................................................................. 293
6.6 Register Descriptions .................................................................................................. 293
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7.1
7.2
7.2.1
7.2.2
7.2.3
7.3
7.4
7.5
Internal Memory ................................................................................................... 310
Block Diagram ............................................................................................................ 310
Functional Description ................................................................................................. 310
SRAM ........................................................................................................................ 311
ROM .......................................................................................................................... 311
Flash Memory ............................................................................................................. 313
Register Map .............................................................................................................. 318
Flash Memory Register Descriptions (Flash Control Offset) ............................................ 320
Memory Register Descriptions (System Control Offset) .................................................. 332
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Micro Direct Memory Access (μDMA) ................................................................ 356
8.1 Block Diagram ............................................................................................................ 357
8.2 Functional Description ................................................................................................. 357
8.2.1 Channel Assignments .................................................................................................. 358
8.2.2 Priority ........................................................................................................................ 359
8.2.3 Arbitration Size ............................................................................................................ 359
8.2.4 Request Types ............................................................................................................ 360
8.2.5 Channel Configuration ................................................................................................. 360
8.2.6 Transfer Modes ........................................................................................................... 362
8.2.7 Transfer Size and Increment ........................................................................................ 370
8.2.8 Peripheral Interface ..................................................................................................... 370
8.2.9 Software Request ........................................................................................................ 370
8.2.10 Interrupts and Errors .................................................................................................... 371
8.3 Initialization and Configuration ..................................................................................... 371
8.3.1 Module Initialization ..................................................................................................... 371
8.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 372
January 23, 2012
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