LM3S5D56 Datasheet, PDF (57/1146 Pages) Texas Instruments – Stellaris® LM3S5D56 Microcontroller

Stellaris^® LM3S5D56 Microcontroller
1.3.4.6
1.3.4.7
Watchdog Timers (see page 513)
A watchdog timer is used to regain control when a system has failed due to a software error or to
the failure of an external device to respond in the expected way. The Stellaris Watchdog Timer can
generate an interrupt or a reset when a time-out value is reached. In addition, the Watchdog Timer
is ARM FiRM-compliant and can be configured to generate an interrupt to the microcontroller on its
first time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has
been configured, the lock register can be written to prevent the timer configuration from being
inadvertently altered.
The LM3S5D56 microcontroller has two Watchdog Timer modules: Watchdog Timer 0 uses the
system clock for its timer clock; Watchdog Timer 1 uses the PIOSC as its timer clock. The Stellaris
Watchdog Timer module has the following features:
■ 32-bit down counter with a programmable load register
■ Separate watchdog clock with an enable
■ Programmable interrupt generation logic with interrupt masking
■ Lock register protection from runaway software
■ Reset generation logic with an enable/disable
■ User-enabled stalling when the microcontroller asserts the CPU Halt flag during debug
Programmable GPIOs (see page 416)
General-purpose input/output (GPIO) pins offer flexibility for a variety of connections. The Stellaris
GPIO module is comprised of five physical GPIO blocks, each corresponding to an individual GPIO
port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP for Real-Time
Microcontrollers specification) and supports 0-33 programmable input/output pins. The number of
GPIOs available depends on the peripherals being used (see “Signal Tables” on page 1047 for the
signals available to each GPIO pin).
■ Up to 33 GPIOs, depending on configuration
■ Highly flexible pin muxing allows use as GPIO or one of several peripheral functions
■ 5-V-tolerant in input configuration
■ Two means of port access: either Advanced High-Performance Bus (AHB) with better back-to-back
access performance, or the legacy Advanced Peripheral Bus (APB) for backwards-compatibility
with existing code
■ Fast toggle capable of a change every clock cycle for ports on AHB, every two clock cycles for
ports on APB
■ Programmable control for GPIO interrupts
– Interrupt generation masking
– Edge-triggered on rising, falling, or both
– Level-sensitive on High or Low values
January 23, 2012
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