LM3S1621 Datasheet, PDF (932/947 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Register Quick Reference
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SSICPSR, type R/W, offset 0x010, reset 0x0000.0000 (see page 756)
SSIIM, type R/W, offset 0x014, reset 0x0000.0000 (see page 757)
CPSDVSR
SSIRIS, type RO, offset 0x018, reset 0x0000.0008 (see page 758)
TXIM
RXIM
RTIM RORIM
SSIMIS, type RO, offset 0x01C, reset 0x0000.0000 (see page 760)
TXRIS RXRIS RTRIS RORRIS
SSIICR, type W1C, offset 0x020, reset 0x0000.0000 (see page 762)
TXMIS RXMIS RTMIS RORMIS
SSIDMACTL, type R/W, offset 0x024, reset 0x0000.0000 (see page 763)
RTIC RORIC
SSIPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 (see page 764)
TXDMAE RXDMAE
SSIPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 (see page 765)
PID4
SSIPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 (see page 766)
PID5
SSIPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 (see page 767)
PID6
SSIPeriphID0, type RO, offset 0xFE0, reset 0x0000.0022 (see page 768)
PID7
SSIPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000 (see page 769)
PID0
SSIPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 (see page 770)
PID1
SSIPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 (see page 771)
PID2
SSIPCellID0, type RO, offset 0xFF0, reset 0x0000.000D (see page 772)
PID3
SSIPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 (see page 773)
CID0
SSIPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 (see page 774)
CID1
CID2
932
January 21, 2012
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