LM3S1621 Datasheet, PDF (14/947 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Table of Contents
List of Tables
Table 1.
Table 2.
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
Table 2-5.
Table 2-6.
Table 2-7.
Table 2-8.
Table 2-9.
Table 2-10.
Table 2-11.
Table 2-12.
Table 2-13.
Table 3-1.
Table 3-2.
Table 3-3.
Table 3-4.
Table 3-5.
Table 3-6.
Table 3-7.
Table 3-8.
Table 3-9.
Table 4-1.
Table 4-2.
Table 4-3.
Table 4-4.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 5-5.
Table 5-6.
Table 5-7.
Table 5-8.
Table 5-9.
Table 6-1.
Table 6-2.
Table 6-3.
Table 6-4.
Table 7-1.
Table 7-2.
Table 7-3.
Table 8-1.
Table 8-2.
Revision History .................................................................................................. 27
Documentation Conventions ................................................................................ 39
Summary of Processor Mode, Privilege Level, and Stack Use ................................ 65
Processor Register Map ....................................................................................... 66
PSR Register Combinations ................................................................................. 71
Memory Map ....................................................................................................... 79
Memory Access Behavior ..................................................................................... 82
SRAM Memory Bit-Banding Regions .................................................................... 84
Peripheral Memory Bit-Banding Regions ............................................................... 84
Exception Types .................................................................................................. 90
Interrupts ............................................................................................................ 90
Exception Return Behavior ................................................................................... 95
Faults ................................................................................................................. 96
Fault Status and Fault Address Registers .............................................................. 97
Cortex-M3 Instruction Summary ........................................................................... 99
Core Peripheral Register Regions ....................................................................... 102
Memory Attributes Summary .............................................................................. 105
TEX, S, C, and B Bit Field Encoding ................................................................... 108
Cache Policy for Memory Attribute Encoding ....................................................... 109
AP Bit Field Encoding ........................................................................................ 109
Memory Region Attributes for Stellaris Microcontrollers ........................................ 109
Peripherals Register Map ................................................................................... 110
Interrupt Priority Levels ...................................................................................... 137
Example SIZE Field Values ................................................................................ 165
JTAG_SWD_SWO Signals (100LQFP) ................................................................ 169
JTAG_SWD_SWO Signals (108BGA) ................................................................. 170
JTAG Port Pins State after Power-On Reset or RST assertion .............................. 171
JTAG Instruction Register Commands ................................................................. 176
System Control & Clocks Signals (100LQFP) ...................................................... 180
System Control & Clocks Signals (108BGA) ........................................................ 180
Reset Sources ................................................................................................... 181
Clock Source Options ........................................................................................ 188
Possible System Clock Frequencies Using the SYSDIV Field ............................... 191
Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 191
Examples of Possible System Clock Frequencies with DIV400=1 ......................... 192
System Control Register Map ............................................................................. 196
RCC2 Fields that Override RCC Fields ............................................................... 217
Hibernate Signals (100LQFP) ............................................................................. 275
Hibernate Signals (108BGA) .............................................................................. 276
Hibernation Module Clock Operation ................................................................... 282
Hibernation Module Register Map ....................................................................... 284
Flash Memory Protection Policy Combinations .................................................... 305
User-Programmable Flash Memory Resident Registers ....................................... 309
Flash Register Map ............................................................................................ 309
μDMA Channel Assignments .............................................................................. 340
Request Type Support ....................................................................................... 342
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January 21, 2012
Texas Instruments-Production Data