LM3S1621 Datasheet, PDF (12/947 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Table of Contents
Figure 15-10. MICROWIRE Frame Format (Single Frame) ........................................................ 744
Figure 15-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 745
Figure 15-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 745
Figure 16-1. I²C Block Diagram ............................................................................................. 777
Figure 16-2. I²C Bus Configuration ........................................................................................ 778
Figure 16-3. START and STOP Conditions ............................................................................. 779
Figure 16-4. Complete Data Transfer with a 7-Bit Address ....................................................... 779
Figure 16-5. R/S Bit in First Byte ............................................................................................ 780
Figure 16-6. Data Validity During Bit Transfer on the I²C Bus ................................................... 780
Figure 16-7. Master Single TRANSMIT .................................................................................. 784
Figure 16-8. Master Single RECEIVE ..................................................................................... 785
Figure 16-9. Master TRANSMIT with Repeated START ........................................................... 786
Figure 16-10. Master RECEIVE with Repeated START ............................................................. 787
Figure 16-11. Master RECEIVE with Repeated START after TRANSMIT with Repeated
START .............................................................................................................. 788
Figure 16-12. Master TRANSMIT with Repeated START after RECEIVE with Repeated
START .............................................................................................................. 789
Figure 16-13. Slave Command Sequence ................................................................................ 790
Figure 17-1. Analog Comparator Module Block Diagram ......................................................... 814
Figure 17-2. Structure of Comparator Unit .............................................................................. 816
Figure 17-3. Comparator Internal Reference Structure ............................................................ 817
Figure 18-1. 100-Pin LQFP Package Pin Diagram .................................................................. 827
Figure 18-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................... 828
Figure 21-1. Load Conditions ................................................................................................ 887
Figure 21-2. JTAG Test Clock Input Timing ............................................................................. 888
Figure 21-3. JTAG Test Access Port (TAP) Timing .................................................................. 888
Figure 21-4. Power-On Reset Timing ..................................................................................... 889
Figure 21-5. Brown-Out Reset Timing .................................................................................... 889
Figure 21-6. Power-On Reset and Voltage Parameters ........................................................... 890
Figure 21-7. External Reset Timing (RST) .............................................................................. 890
Figure 21-8. Software Reset Timing ....................................................................................... 890
Figure 21-9. Watchdog Reset Timing ..................................................................................... 891
Figure 21-10. MOSC Failure Reset Timing ............................................................................... 891
Figure 21-11. Hibernation Module Timing with Internal Oscillator Running in Hibernation ............ 895
Figure 21-12. Hibernation Module Timing with Internal Oscillator Stopped in Hibernation ............ 896
Figure 21-13. SDRAM Initialization and Load Mode Register Timing .......................................... 897
Figure 21-14. SDRAM Read Timing ......................................................................................... 898
Figure 21-15. SDRAM Write Timing ......................................................................................... 898
Figure 21-16. Host-Bus 8/16 Mode Read Timing ...................................................................... 899
Figure 21-17. Host-Bus 8/16 Mode Write Timing ....................................................................... 899
Figure 21-18. Host-Bus 8/16 Mode Muxed Read Timing ............................................................ 900
Figure 21-19. Host-Bus 8/16 Mode Muxed Write Timing ............................................................ 900
Figure 21-20. General-Purpose Mode Read and Write Timing ................................................... 901
Figure 21-21. General-Purpose Mode iRDY Timing .................................................................. 901
Figure 21-22. ADC Input Equivalency Diagram ......................................................................... 903
Figure 21-23. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................... 904
Figure 21-24. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 904
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January 21, 2012
Texas Instruments-Production Data