LM3S1621 Datasheet, PDF (25/947 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Stellaris^® LM3S1621 Microcontroller
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Register 54:
ADC Digital Comparator Control 0 (ADCDCCTL0), offset 0xE00 ....................................... 667
ADC Digital Comparator Control 1 (ADCDCCTL1), offset 0xE04 ....................................... 667
ADC Digital Comparator Control 2 (ADCDCCTL2), offset 0xE08 ....................................... 667
ADC Digital Comparator Control 3 (ADCDCCTL3), offset 0xE0C ...................................... 667
ADC Digital Comparator Control 4 (ADCDCCTL4), offset 0xE10 ....................................... 667
ADC Digital Comparator Control 5 (ADCDCCTL5), offset 0xE14 ....................................... 667
ADC Digital Comparator Control 6 (ADCDCCTL6), offset 0xE18 ....................................... 667
ADC Digital Comparator Control 7 (ADCDCCTL7), offset 0xE1C ...................................... 667
ADC Digital Comparator Range 0 (ADCDCCMP0), offset 0xE40 ....................................... 669
ADC Digital Comparator Range 1 (ADCDCCMP1), offset 0xE44 ....................................... 669
ADC Digital Comparator Range 2 (ADCDCCMP2), offset 0xE48 ....................................... 669
ADC Digital Comparator Range 3 (ADCDCCMP3), offset 0xE4C ...................................... 669
ADC Digital Comparator Range 4 (ADCDCCMP4), offset 0xE50 ....................................... 669
ADC Digital Comparator Range 5 (ADCDCCMP5), offset 0xE54 ....................................... 669
ADC Digital Comparator Range 6 (ADCDCCMP6), offset 0xE58 ....................................... 669
ADC Digital Comparator Range 7 (ADCDCCMP7), offset 0xE5C ...................................... 669
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 670
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 685
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 687
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 690
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 693
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 694
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 695
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 696
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 698
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 702
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 704
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 708
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 712
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 716
Register 14: UART DMA Control (UARTDMACTL), offset 0x048 .......................................................... 718
Register 15: UART LIN Control (UARTLCTL), offset 0x090 ................................................................. 719
Register 16: UART LIN Snap Shot (UARTLSS), offset 0x094 ............................................................... 720
Register 17: UART LIN Timer (UARTLTIM), offset 0x098 ..................................................................... 721
Register 18: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 722
Register 19: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 723
Register 20: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 724
Register 21: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 725
Register 22: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 726
Register 23: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 727
Register 24: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 728
Register 25: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 729
Register 26: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 730
Register 27: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 731
Register 28: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 732
Register 29: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 733
Synchronous Serial Interface (SSI) ............................................................................................ 734
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 749
January 21, 2012
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