LM3S1621 Datasheet, PDF (462/947 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

External Peripheral Interface (EPI)
Figure 10-2. SDRAM Non-Blocking Read Cycle
CLK
(EPI0S31)
CKE
(EPI0S30)
CSn
(EPI0S29)
WEn
(EPI0S28)
RASn
(EPI0S19)
CASn
(EPI0S18)
DQMH, DQML
(EPI0S [17:16])
AD [15:0]
(EPI0S [15:0])
Row
Activate
NOP
NOP
Column
Read
NOP
AD [15:0] driven out
AD [15:0] driven out
Data 0
Data 1
...
Burst
Term
AD [15:0] driven in
Data n
10.4.1.5
Normal Read Cycle
Figure 10-3 on page 462 shows a normal read cycle of n halfwords; n can be 1 or 2. The cycle begins
with the Activate command and the row address on the EPI0S[15:0] signals. With the programmed
CAS latency of 2, the Read command with the column address on the EPI0S[15:0] signals follows
after 2 clock cycles. Following one more NOP cycle, data is read in on the EPI0S[15:0] signals
on every rising clock edge. The DQMH, DQML, and CSn signals are deasserted after the last
halfword of data is received, signaling the end of the cycle. At least one clock period of inactivity
separates any two SDRAM cycles.
Figure 10-3. SDRAM Normal Read Cycle
CLK
(EPI0S31)
CKE
(EPI0S30)
CSn
(EPI0S29)
WEn
(EPI0S28)
RASn
(EPI0S19)
CASn
(EPI0S18)
DQMH, DQML
(EPI0S [17:16])
AD [15:0]
(EPI0S [15:0])
Row
Activate
NOP
AD [15:0] driven out
NOP
Column
Read
NOP
AD [15:0] driven out
Data 0
Data 1
AD [15:0] driven in
462
January 21, 2012
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