LM3S1621 Datasheet, PDF (836/947 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Signal Tables
Table 19-2. Signals by Pin Number (continued)
Pin Number
Pin Name
Pin Type Buffer Type^a Description
PC0
I/O
TTL
GPIO port C bit 0.
80
SWCLK
I
TTL
JTAG/SWD CLK.
TCK
I
TTL
JTAG/SWD CLK.
81
VDD
-
Power Positive supply for I/O and some logic.
82
GND
-
Power Ground reference for logic and I/O pins.
PH3
I/O
TTL
GPIO port H bit 3.
83
EPI0S0
I/O
TTL
EPI module 0 signal 0.
PH2
I/O
TTL
GPIO port H bit 2.
84
C1o
O
TTL
Analog comparator 1 output.
EPI0S1
I/O
TTL
EPI module 0 signal 1.
PH1
I/O
TTL
GPIO port H bit 1.
85
CCP7
I/O
TTL
Capture/Compare/PWM 7.
EPI0S7
I/O
TTL
EPI module 0 signal 7.
PH0
I/O
TTL
GPIO port H bit 0.
86
CCP6
I/O
TTL
Capture/Compare/PWM 6.
EPI0S6
I/O
TTL
EPI module 0 signal 6.
PJ1
I/O
TTL
GPIO port J bit 1.
87
EPI0S17
I/O
TTL
EPI module 0 signal 17.
I2C1SDA
I/O
OD
I²C module 1 data.
VDDC
88
-
Power Positive supply for most of the logic function, including the
processor core and most peripherals. The voltage on this pin is
1.3 V and is supplied by the on-chip LDO. The VDDC pins should
only be connected to the LDO pin and an external capacitor as
specified in Table 21-6 on page 891.
PB7
I/O
TTL
GPIO port B bit 7.
89
NMI
I
TTL
Non-maskable interrupt.
PB6
I/O
TTL
GPIO port B bit 6.
C0+
I
Analog Analog comparator 0 positive input.
C0o
O
TTL
Analog comparator 0 output.
CCP1
I/O
TTL
Capture/Compare/PWM 1.
CCP5
I/O
TTL
Capture/Compare/PWM 5.
90
CCP7
I/O
TTL
Capture/Compare/PWM 7.
VREFA
I
Analog This input provides a reference voltage used to specify the input
voltage at which the ADC converts to a maximum value. In other
words, the voltage that is applied to VREFA is the voltage with which
an AINn signal is converted to 1023. The VREFA input is limited
to the range specified in Table 21-26 on page 903 .
836
January 21, 2012
Texas Instruments-Production Data