LM3S1621 Datasheet, PDF (10/947 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Table of Contents
List of Figures
Figure 1-1. Stellaris LM3S1621 Microcontroller High-Level Block Diagram ............................... 42
Figure 2-1. CPU Block Diagram ............................................................................................. 62
Figure 2-2. TPIU Block Diagram ............................................................................................ 63
Figure 2-3. Cortex-M3 Register Set ........................................................................................ 65
Figure 2-4. Bit-Band Mapping ................................................................................................ 85
Figure 2-5. Data Storage ....................................................................................................... 86
Figure 2-6. Vector Table ........................................................................................................ 92
Figure 2-7. Exception Stack Frame ........................................................................................ 94
Figure 3-1. SRD Use Example ............................................................................................. 108
Figure 4-1. JTAG Module Block Diagram .............................................................................. 169
Figure 4-2. Test Access Port State Machine ......................................................................... 172
Figure 4-3. IDCODE Register Format ................................................................................... 178
Figure 4-4. BYPASS Register Format ................................................................................... 178
Figure 4-5. Boundary Scan Register Format ......................................................................... 179
Figure 5-1. Basic RST Configuration .................................................................................... 183
Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 183
Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 184
Figure 5-4. Power Architecture ............................................................................................ 187
Figure 5-5. Main Clock Tree ................................................................................................ 190
Figure 6-1. Hibernation Module Block Diagram ..................................................................... 275
Figure 6-2. Using a Crystal as the Hibernation Clock Source ................................................. 278
Figure 6-3. Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON
Mode ................................................................................................................ 278
Figure 7-1. Internal Memory Block Diagram .......................................................................... 301
Figure 8-1. μDMA Block Diagram ......................................................................................... 339
Figure 8-2. Example of Ping-Pong μDMA Transaction ........................................................... 345
Figure 8-3. Memory Scatter-Gather, Setup and Configuration ................................................ 347
Figure 8-4. Memory Scatter-Gather, μDMA Copy Sequence .................................................. 348
Figure 8-5. Peripheral Scatter-Gather, Setup and Configuration ............................................. 350
Figure 8-6. Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 351
Figure 9-1. Digital I/O Pads ................................................................................................. 401
Figure 9-2. Analog/Digital I/O Pads ...................................................................................... 402
Figure 9-3. GPIODATA Write Example ................................................................................. 403
Figure 9-4. GPIODATA Read Example ................................................................................. 403
Figure 10-1. EPI Block Diagram ............................................................................................. 454
Figure 10-2. SDRAM Non-Blocking Read Cycle ...................................................................... 462
Figure 10-3. SDRAM Normal Read Cycle ............................................................................... 462
Figure 10-4. SDRAM Write Cycle ........................................................................................... 463
Figure 10-5. Example Schematic for Muxed Host-Bus 16 Mode ............................................... 469
Figure 10-6. Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 471
Figure 10-7. Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 472
Figure 10-8. Host-Bus Write Cycle with Multiplexed Address and Data, MODE = 0x0, WRHIGH
= 0, RDHIGH = 0 ............................................................................................... 472
Figure 10-9. Host-Bus Write Cycle with Multiplexed Address and Data and ALE with Dual
CSn .................................................................................................................. 473
Figure 10-10. Continuous Read Mode Accesses ...................................................................... 473
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January 21, 2012
Texas Instruments-Production Data