LM3S1621 Datasheet, PDF (534/947 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

General-Purpose Timers
Figure 11-3. Input Edge-Count Mode Example
Count
Timer stops,
flags
asserted
Timer reload
on next cycle Ignored
Ignored
0x000A
0x0009
0x0008
0x0007
0x0006
Input Signal
11.3.2.4
Input Edge-Time Mode
Note:
For rising-edge detection, the input signal must be High for at least two system clock periods
following the rising edge. Similarly, for falling edge detection, the input signal must be Low
for at least two system clock periods following the falling edge. Based on this criteria, the
maximum input frequency for edge detection is 1/4 of the system frequency.
The prescaler is not available in 16-Bit Input Edge-Time mode.
In Edge-Time mode, the timer is configured as a 16-bit down-counter. In this mode, the timer is
initialized to the value loaded in the GPTMTnILRregister. The timer is capable of capturing three
types of events: rising edge, falling edge, or both. The timer is placed into Edge-Time mode by
setting the TnCMR bit in the GPTMTnMR register, and the type of event that the timer captures is
determined by the TnEVENT fields of the GPTMCTL register. Table 11-9 on page 534 shows the
values that are loaded into the timer registers when the timer is enabled.
Table 11-9. Counter Values When the Timer is Enabled in Input Event-Count Mode
Register
TnR
TnV
Count Down Mode
GPTMTnILR
GPTMTnILR
Count Up Mode
Not available
Not available
When software writes the TnEN bit in the GPTMCTL register, the timer is enabled for event capture.
When the selected input event is detected, the current timer counter value is captured in the
GPTMTnR register and is available to be read by the microcontroller. The GPTM then asserts the
CnERIS bit in the GPTM Raw Interrupt Status (GPTMRIS) register, and holds it until it is cleared
by writing the GPTM Interrupt Clear (GPTMICR) register. If the capture mode event interrupt is
enabled in the GPTM Interrupt Mask (GPTMIMR) register, the GPTM also sets the CnEMIS bit in
the GPTM Masked Interrupt Status (GPTMMIS) register. In this mode, the GPTMTnR register
holds the time at which the selected input event occurred while the GPTMTnV register holds the
free-running timer value. These registers can be read to determine the time that elapsed between
the interrupt assertion and the entry into the ISR.
534
January 21, 2012
Texas Instruments-Production Data