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Analog-to-Digital Converter (ADC)
Figure 13-13. High-Band Operation (CIC=0x3)
COMP1
COMP0
Always – 0 0 0 0 1 1 1 0 0 1 1 0 0 0 1 1
Once – 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0
Hysteresis Always – 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1
Hysteresis Once – 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0
13.4
13.4.1
Initialization and Configuration
In order for the ADC module to be used, the PLL must be enabled and programmed to a supported
crystal frequency in the RCC register (see page 210). Using unsupported frequencies can cause
faulty operation in the ADC module.
Module Initialization
Initialization of the ADC module is a simple process with very few steps: enabling the clock to the
ADC, disabling the analog isolation circuit associated with all inputs that are to be used, and
reconfiguring the sample sequencer priorities (if needed).
The initialization sequence for the ADC is as follows:
1. Enable the ADC clock by using the RCGC0 register (see page 246).
2. Enable the clock to the appropriate GPIO modules via the RCGC2 register (see page 261). To
find out which GPIO ports to enable, refer to “Signal Description” on page 598.
3. Set the GPIO AFSEL bits for the ADC input pins (see page 420). To determine which GPIOs to
configure, see Table 19-4 on page 845.
4. Configure the AINx and VREFA signals to be analog inputs by clearing the corresponding DEN
bit in the GPIO Digital Enable (GPIODEN) register (see page 431).
5. Disable the analog isolation circuit for all ADC input pins that are to be used by writing a 1 to
the appropriate bits of the GPIOAMSEL register (see page 436) in the associated GPIO block.
612
January 21, 2012
Texas Instruments-Production Data