LM3S1621 Datasheet, PDF (602/947 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Analog-to-Digital Converter (ADC)
13.3.2.5
Sample Phase Control
The sample time can be delayed from the standard sampling time in 22.5° increments up to 337.5º
using the ADC Sample Phase Control (ADCSPC) register. Figure 13-2 on page 602 shows an
example of various phase relationships at a 1 Msps rate.
Figure 13-2. ADC Sample Phases
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
ADC Sample Clock
PHASE 0x0 (0.0°)
PHASE 0x1 (22.5°)
.
.
.
.
.
.
PHASE 0xE (315.0°)
.
.
.
.
.
.
PHASE 0xF (337.5°)
13.3.3
Hardware Sample Averaging Circuit
Higher precision results can be generated using the hardware averaging circuit, however, the
improved results are at the cost of throughput. Up to 64 samples can be accumulated and averaged
to form a single data entry in the sequencer FIFO. Throughput is decreased proportionally to the
number of samples in the averaging calculation. For example, if the averaging circuit is configured
to average 16 samples, the throughput is decreased by a factor of 16.
By default the averaging circuit is off, and all data from the converter passes through to the sequencer
FIFO. The averaging hardware is controlled by the ADC Sample Averaging Control (ADCSAC)
register (see page 636). A single averaging circuit has been implemented, thus all input channels
receive the same amount of averaging whether they are single-ended or differential.
Figure 13-3 shows an example in which the ADCSAC register is set to 0x2 for 4x hardware
oversampling and the IE1 bit is set for the sample sequence, resulting in an interrupt after the
second averaged value is stored in the FIFO.
602
January 21, 2012
Texas Instruments-Production Data