LM3S1621 Datasheet, PDF (540/947 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

General-Purpose Timers
11.4.5
PWM Mode
A timer is configured to PWM mode using the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x0000.0004.
3. In the GPTM Timer Mode (GPTMTnMR) register, set the TnAMS bit to 0x1, the TnCMR bit to
0x0, and the TnMR field to 0x2.
4. Configure the output state of the PWM signal (whether or not it is inverted) in the TnPWML field
of the GPTM Control (GPTMCTL) register.
5. Load the timer start value into the GPTM Timer n Interval Load (GPTMTnILR) register.
6. Load the GPTM Timer n Match (GPTMTnMATCHR) register with the match value.
7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin
generation of the output PWM signal.
In PWM Timing mode, the timer continues running after the PWM signal has been generated. The
PWM period can be adjusted at any time by writing the GPTMTnILR register, and the change takes
effect at the next cycle after the write.
11.5
Register Map
Table 11-11 on page 540 lists the GPTM registers. The offset listed is a hexadecimal increment to
the register’s address, relative to that timer’s base address:
■ Timer 0: 0x4003.0000
■ Timer 1: 0x4003.1000
■ Timer 2: 0x4003.2000
■ Timer 3: 0x4003.3000
Note that the GP Timer module clock must be enabled before the registers can be programmed
(see page 252). There must be a delay of 3 system clocks after the Timer module clock is enabled
before any Timer module registers are accessed.
Table 11-11. Timers Register Map
Offset Name
Type
0x000 GPTMCFG
0x004 GPTMTAMR
0x008 GPTMTBMR
0x00C GPTMCTL
0x018 GPTMIMR
0x01C GPTMRIS
0x020 GPTMMIS
0x024 GPTMICR
R/W
R/W
R/W
R/W
R/W
RO
RO
W1C
Reset
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
Description
GPTM Configuration
GPTM Timer A Mode
GPTM Timer B Mode
GPTM Control
GPTM Interrupt Mask
GPTM Raw Interrupt Status
GPTM Masked Interrupt Status
GPTM Interrupt Clear
See
page
542
543
545
547
550
552
555
558
540
January 21, 2012
Texas Instruments-Production Data