LM3S1621 Datasheet, PDF (928/947 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

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0
ADCSSFSTAT3, type RO, offset 0x0AC, reset 0x0000.0100 (see page 646)
FULL
ADCSSOP0, type R/W, offset 0x050, reset 0x0000.0000 (see page 648)
S7DCOP
S3DCOP
ADCSSDC0, type R/W, offset 0x054, reset 0x0000.0000 (see page 650)
S7DCSEL
S6DCSEL
S3DCSEL
S2DCSEL
ADCSSMUX1, type R/W, offset 0x060, reset 0x0000.0000 (see page 652)
EMPTY
S6DCOP
S2DCOP
HPTR
S5DCOP
S1DCOP
S5DCSEL
S1DCSEL
TPTR
S4DCOP
S0DCOP
S4DCSEL
S0DCSEL
MUX3
MUX2
ADCSSMUX2, type R/W, offset 0x080, reset 0x0000.0000 (see page 652)
MUX1
MUX0
MUX3
MUX2
ADCSSCTL1, type R/W, offset 0x064, reset 0x0000.0000 (see page 653)
MUX1
MUX0
TS3
IE3
END3
D3
TS2
IE2
END2
D2
TS1
IE1
END1
D1
TS0
IE0
END0
D0
ADCSSCTL2, type R/W, offset 0x084, reset 0x0000.0000 (see page 653)
TS3
IE3
END3
D3
TS2
IE2
END2
D2
TS1
IE1
END1
D1
TS0
IE0
END0
D0
ADCSSOP1, type R/W, offset 0x070, reset 0x0000.0000 (see page 655)
S3DCOP
ADCSSOP2, type R/W, offset 0x090, reset 0x0000.0000 (see page 655)
S2DCOP
S1DCOP
S0DCOP
S3DCOP
ADCSSDC1, type R/W, offset 0x074, reset 0x0000.0000 (see page 656)
S2DCOP
S1DCOP
S0DCOP
S3DCSEL
S2DCSEL
ADCSSDC2, type R/W, offset 0x094, reset 0x0000.0000 (see page 656)
S1DCSEL
S0DCSEL
S3DCSEL
S2DCSEL
ADCSSMUX3, type R/W, offset 0x0A0, reset 0x0000.0000 (see page 658)
S1DCSEL
S0DCSEL
ADCSSCTL3, type R/W, offset 0x0A4, reset 0x0000.0002 (see page 659)
MUX0
ADCSSOP3, type R/W, offset 0x0B0, reset 0x0000.0000 (see page 660)
TS0
IE0
END0
D0
ADCSSDC3, type R/W, offset 0x0B4, reset 0x0000.0000 (see page 661)
S0DCOP
ADCDCRIC, type R/W, offset 0xD00, reset 0x0000.0000 (see page 662)
ADCDCCTL0, type R/W, offset 0xE00, reset 0x0000.0000 (see page 667)
S0DCSEL
DCTRIG7 DCTRIG6 DCTRIG5 DCTRIG4 DCTRIG3 DCTRIG2 DCTRIG1 DCTRIG0
DCINT7 DCINT6 DCINT5 DCINT4 DCINT3 DCINT2 DCINT1 DCINT0
CIE
CIC
CIM
928
January 21, 2012
Texas Instruments-Production Data