LM3S1621 Datasheet, PDF (192/947 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

System Control
5.2.5.3
Table 5-6. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field
(continued)
SYSDIV2
Divisor Frequency
(BYPASS2=0)
Frequency (BYPASS2=1)
StellarisWare Parameter^a
0x3F
/64 3.125 MHz
Clock source frequency/64
SYSCTL_SYSDIV_64
a. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library.
b. SYSCTL_SYSDIV_1 does not set the USESYSDIV bit. As a result, using this parameter without enabling the PLL results
in the system clock having the same frequency as the clock source.
To allow for additional frequency choices when using the PLL, the DIV400 bit is provided along
with the SYSDIV2LSB bit. When the DIV400 bit is set, bit 22 becomes the LSB for SYSDIV2. In
this situation, the divisor is equivalent to the (SYSDIV2 encoding with SYSDIV2LSB appended) plus
one. Table 5-7 shows the frequency choices when DIV400 is set. When the DIV400 bit is clear,
SYSDIV2LSB is ignored, and the system clock frequency is determined as shown in Table
5-6 on page 191.
Table 5-7. Examples of Possible System Clock Frequencies with DIV400=1
SYSDIV2 SYSDIV2LSB
Divisor
Frequency (BYPASS2=0)^a
StellarisWare Parameter^b
0x00
reserved
/2
reserved
-
0
/3
reserved
-
0x01
1
/4
reserved
-
0
0x02
1
/5
80 MHz
/6
66.67 MHz
SYSCTL_SYSDIV_2_5
SYSCTL_SYSDIV_3
0
0x03
1
/7
reserved
/8
50 MHz
-
SYSCTL_SYSDIV_4
0
0x04
1
/9
44.44 MHz
/10
40 MHz
SYSCTL_SYSDIV_4_5
SYSCTL_SYSDIV_5
...
...
...
...
...
0
0x3F
1
/127
3.15 MHz
/128
3.125 MHz
SYSCTL_SYSDIV_63_5
SYSCTL_SYSDIV_64
a. Note that DIV400 and SYSDIV2LSB are only valid when BYPASS2=0.
b. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library.
Precision Internal Oscillator Operation (PIOSC)
The microcontroller powers up with the PIOSC running. If another clock source is desired, the PIOSC
must remain enabled as it is used for internal functions. The PIOSC can only be disabled during
Deep-Sleep mode. It can be powered down by setting the IOSCDIS bit in the RCC register.
The PIOSC generates a 16-MHz clock with a ±1% accuracy at room temperatures. Across the
extended temperature range, the accuracy is ±3%. At the factory, the PIOSC is set to 16 MHz at
room temperature, however, the frequency can be trimmed for other voltage or temperature conditions
using software in one of three ways:
■ Default calibration: clear the UTEN bit and set the UPDATE bit in the Precision Internal Oscillator
Calibration (PIOSCCAL) register.
■ User-defined calibration: The user can program the UT value to adjust the PIOSC frequency. As
the UT value increases, the generated period increases. To commit a new UT value, first set the
192
January 21, 2012
Texas Instruments-Production Data