LM3S1621 Datasheet, PDF (26/947 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Table of Contents
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 751
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 753
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 754
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 756
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 757
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 758
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 760
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 762
Register 10: SSI DMA Control (SSIDMACTL), offset 0x024 ................................................................. 763
Register 11: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 764
Register 12: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 765
Register 13: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 766
Register 14: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 767
Register 15: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 768
Register 16: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 769
Register 17: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 770
Register 18: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 771
Register 19: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 772
Register 20: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 773
Register 21: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 774
Register 22: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 775
Inter-Integrated Circuit (I²C) Interface ........................................................................................ 776
Register 1: I²C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 793
Register 2: I²C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 794
Register 3: I²C Master Data (I2CMDR), offset 0x008 ......................................................................... 799
Register 4: I²C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 800
Register 5: I²C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 801
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
I²C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 802
I²C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 803
I²C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 804
I²C Master Configuration (I2CMCR), offset 0x020 ............................................................ 805
I²C Slave Own Address (I2CSOAR), offset 0x800 ............................................................ 806
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
I²C Slave Control/Status (I2CSCSR), offset 0x804 ........................................................... 807
I²C Slave Data (I2CSDR), offset 0x808 ........................................................................... 809
I²C Slave Interrupt Mask (I2CSIMR), offset 0x80C ........................................................... 810
I²C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 ................................................... 811
I²C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 .............................................. 812
Register 16: I²C Slave Interrupt Clear (I2CSICR), offset 0x818 ............................................................ 813
Analog Comparators ................................................................................................................... 814
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 .................................. 820
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 ....................................... 821
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 ......................................... 822
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 ....................... 823
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020 ..................................................... 824
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x040 ..................................................... 824
Register 7: Analog Comparator Control 0 (ACCTL0), offset 0x024 ..................................................... 825
Register 8: Analog Comparator Control 1 (ACCTL1), offset 0x044 ..................................................... 825
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January 21, 2012
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