TLK2226_09 Datasheet, PDF (9/52 Pages) Texas Instruments – 6 PORT GIGABIT ETHERNET TRANSCEIVER

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TLK2226
SLLS689D – JANUARY 2006 – REVISED DECEMBER 2006
RCLK[A−F]
RDx[4:0]
Thdav
Tsuav
LSB Nibble
Thdav
VDDQ/2
Tsuav
MSB Nibble
Figure 8. HSTL Receive Output Timing Requirements (Aligned)
HSTL INPUT TIMING REQUIREMENTS
over recommended operating conditions (unless otherwise noted)
T_ISU
T_IHD
T_suav
T_hdav
PARAMETER
TEST CONDITION
TDx[4:0] setup prior to TCLK transition
high or low
Figure 19 timing relative to 0.5×VDDQ,
25 MHz and 125 MHz
TDx[4:0] hold after TCLK transition high or Figure 19, timing relative to 0.5×VDDQ,
low
25 MHz and 125 MHz
RCLK transition high or low to data valid Figure 18, timing relative to 0.5×VDDQ,
window beginning (RD[4:0]).
25 MHz and 125 MHz
RCLK transition high or low to data valid Figure 18, timing relative to 0.5×VDDQ,
window ending (RD[4:0]).
25 MHz and 125 MHz
(1) All typical values are at 25°C and with a nominal supply.
MIN TYP⁽¹⁾
0.6
MAX UNIT
ns
0.6
ns
1.4 ns
2.6
ns
TCLKx
tr
TDx[4:0]
VDDQ/2
tf
tISU
tIHD
tISU
tIHD
LSB Nibble
MSB Nibble
Figure 9. HSTL Data Input Timing Requirements (Centered)
TCLK[A−F]
TDx[4:0]
Thdav
Tsuav
LSB Nibble
Thdav
VDDQ/2
Tsuav
MSB Nibble
Figure 10. HSTL Data Input Timing Requirements (Aligned)
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