TLK2226_09 Datasheet, PDF (34/52 Pages) Texas Instruments – 6 PORT GIGABIT ETHERNET TRANSCEIVER

TLK2226
SLLS689D – JANUARY 2006 – REVISED DECEMBER 2006
www.ti.com
Table 18. (Vendor Specific) CH Control 1 Register (0x11) Bit Definitions
Bit(s) Default Value
17.15 1B’0
17.14 1B’0
17.13 1’B1
17.12 1’B1
17.11: 3B’111
9
17.8 1B’1
17.7 1B’0
17.6 1’B0
17.5 1B’0
17.4 1B’0
17.3 1’B1
17.2 1’B1
17.1 1B’1
17.0 1B’1
Name
Global write
Sync Status
Override
TX PMA Bit
Order
RX PMA Bit
Order
Reserved
Description
Read/Write
When written as 1 the settings in 17.14:0 will affect all channels of one
device simultaneously.
When written as 0 the settings in 17.14:0 are only valid for the addressed
channel. This bit always reads zero.
Read/Write
Self Clearing
1 = Causes an override of the sync state 1000Base-X synchronization state Read/Write
machine to reflect a “1” in the sync_1GX (25.14) bit.
0 = Original (normal operation) sync_1GX value is represented in bit 25.14.
(Default)
When asserted, allows the ten bits of data given to the parallel side of the
SERDES TX macro to be flipped. This is normally set since the SERDES
transmits MSB first, and the 1000Base-X standard requires LSB to be
transmitted first. For standard based operation, the customer may leave
this bit alone.
Read/Write
When asserted, allows the ten bits of data received from the parallel side of Read/Write
the SERDES RX macro to be flipped. This is normally set since the
SERDES receives MSB first, and the 1000Base-X standard requires LSB to
be received first. For standard based operation, the customer may leave
this bit alone.
Reserved for TI test.
Read/Write
RX_LOCKREFN 1 = Enables clock recovery loop to lock onto incoming data rate.
Read/Write
0 = Clock recovery loop ignores incoming data rate and locks to REFCLK.
Reserved
Reserved for TI test.
Read/Write
Channel Soft
Reset
1 = Resets channel logic excluding MDIO registers.
Read/Write
Self-Clearing
Reserved
Reserved for TI test.
Read Only
TX Datapath
Override
1 = Allows Transmit Datapath to Send Normal Data Traffic Regardless of Read/Write
Errors in the Receive Datapath (In 1000Base-X Mode,
Auto-Negotiation should also be disabled).
0 = Normal Chip Operation (Standard Based)
PCS 1GX TX
Enable
1 = Enables 1000Base-X PCS TX Function
Read/Write
0 = Disables 1000Base-X PCS TX Function
PCS 1GX Rx
Enable
1 = Enables 1000Base-X PCS Rx Function
Read/Write
0 = Disables 1000Base-X PCS Rx Function
TX Source
Centered
0 = Source synchronous timing on transmit parallel interface. Data is
latched 2ns after clock edge.
Read/Write
1 = Source centered timing on transmit parallel interface. Data is latched
at clock edge.
RX Source
Centered
0 = Source synchronous timing on receive parallel interface. Data
changes at clock edge.
Read/Write
1 = Source centered timing on receive parallel interface. Data changes
2ns after clock edge.
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